Research

Research Interests

Computer Architecture - Memory Hierarchy - Cache and Main Memory
Exploring techniques to improve the performance and/or energy efficiency of different components in the memory hierarchy.

  • Doctoral Research:
    Thesis title: Addressing performance and energy-efficiency issues in high-density DDR4 DRAM based main memory in a multi-core system. Extended abstract
  • Post Graduation Research (during MS by Research):
    Thesis title: Word-Interleaved Cache Architecture pdf

Publications

  • Venkata Kalyan Tavva, Ravi Kasha and Madhu Mutyam. "EFGR: An Enhanced Fine Granularity Refresh Feature for High Performance DDR4 DRAM Devices." ACM Transactions on Architecture and Code Optimization (TACO), 2014. Volume: 11, Issue: 3, Article: 31. link (Invited to make a presentation in the HiPEAC-2015 Conference, Amsterdam, Netherlands, Jan 2015.)
  • Pritam Majumder, Venkata Kalyan Tavva and Madhu Mutyam. "SFFMap: Set-First Fill Mapping for an Energy Efficient Pipelined Data Cache." In the proceedings of IEEE International Conference on Computer Design (ICCD), 2014. PP:104-109. link
  • Sudharsan J, Venkata Kalyan Tavva and Madhu Mutyam. "Data Remapping for an Energy Efficient Burst Chop in DRAM Memory Systems." Received bronze medal in ACM Student Research Competition (ACM SRC), held along with International Conference on Parallel Architectures and Compilation Techniques (PACT), 2014. PP: 507 - 508. link
  • Venkata Kalyan Tavva, Ravi Kasha and Madhu Mutyam. "Scattered Refresh: An Alternative Refresh Mechanism to Reduce Refresh Cycle Time." In the proceedings of IEEE/ACM Asia and South Pacifc Design Automation Conference (ASPDAC), 2014. PP: 598-603.link
  • C. J. Janraj, Venkata Kalyan Tavva, Tripti Warrier and Madhu Mutyam. "Way sharing set associative cache architecture". In the proceedings of International Conference on VLSI Design (VLSID), 2012. PP: 251-256.link
  • Venkata Kalyan Tavva and Madhu Mutyam. "Word-interleaved cache: an energy efficient data cache architecture". In the proceedings of International Symposium on Low Power Electronics and Design (ISLPED), 2008. PP: 265-270.link
  • Venkata Kalyan Tavva, Madhu Mutyam and Vijaya Sankara Rao P. "Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design". In the proceedings of International Conference on VLSI Design (VLSID), 2008. PP 235-241.link

Professional Service

  • Reviewer for VLSID'15.
  • External Reviewer for ICCD'14.

Architectural Simulators used -

  • MARSSx86- Micro-ARchitectural and System Simulator for x86-based Systems
  • DRAMSim2 - JEDEC DDRx memory system simulator
  • USIMM - the Utah SImulated Memory Module
  • Multi2Sim - A Heterogeneous System Simulator
  • CACTI - Cache and DRAM access time, area and power (both dynamic and leakage) model

Computer Architecture - Few important Conferences and Journals