|Title||:||Exploiting Half Block Mapping for Energy Efficient DRAM Memory Systems|
|Speaker||:||Sudharsan J (IITM)|
|Details||:||Tue, 14 Jun, 2016 3:00 PM @ BSB 361|
|Abstract:||:||In current multi-core systems, DRAM-based main memory contributes to 25%-40% of the overall system power consumption. Though JEDEC DDR4 standard provides new features to reduce the power consumption, there is scope for further power reduction.
The rate of growth of the processor technology is very high when compared to the rate of growth of the DRAM-based memory technology. As a result, the main memory access latency is one of the major bottlenecks in determining the overall system performance. This is termed as the Memory Wall. Due to this problem, the data obtained from the memory has to be used judiciously. We observe that a significant fraction of the read/write accesses made to the cache blocks spans over only one half of the block width. We term this phenomenon as half-access. We exploit half-accesses to propose a new technique for mapping the words of a cache block to the DRAM devices. Our proposed mapping, namely, Half Block Mapping (HBM), needs fewer DRAM devices during half-accesses, thereby resulting in reduced memory power consumption. When we employ HBM for exploiting the half-write accesses, we obtain an average saving of 8.89% in the DRAM energy delay product (EDP), compared to the conventional mapping. As the access pattern of memory reads is not known in advance, we employ one of the state-of-the-art predictors, namely, the Spatial Pattern Predictor (SPP) to get the access pattern. With the help of SPP, when we consider half-read accesses as well, we observe an average EDP savings of 18.29%. We also show the efficacy of HBM for DRAM devices that have support for Error-Correcting Code (ECC). Furthermore, HBM requires minimal changes to the existing DRAM design. The simplicity of our design makes it a viable choice for implementation by the industry.