|Title||:||Area and Power estimation of combinational circuits using Fourier analysis|
|Speaker||:||Devakar Kumar Verma (IITM)|
|Details||:||Tue, 26 Apr, 2016 3:00 PM @ BSB 361|
|Abstract:||:||The rapid revolution in the technology results advancement in the complexity of the circuits. A complex logic functions require more space on the chip and incurs high manufacturing cost in terms of time and money. With the rise in the complexity of circuits, the power dissipation emerged as one of the signicant design constraint in the design process. Hence, the area and power estimation in the early phase of design process is becoming more important. The prior information about area and power of the circuit is quite useful in floor planning, chip planning, high-level synthesis and various other architectural explorations.
Our work address the problem of area estimation and power estimation of combinational boolean circuits given only its functional description. We have proposed models to estimate area and power of circuits based on the theory of Fourier analysis of Boolean functions. Our method does not require mapping to logical gates. We demonstrate how the area required by a Boolean function can be captured by the energy distribution in the Fourier spectrum of it. We also demonstrate how the switching activity and dynamic power of the circuit can be captured by the Fourier coecients(or Fourier weights) of the corresponding function. Since Fourier analysis is expensive, we propose models to simplify the analysis by combining Fourier energies appropriately and by partitioning a simplistic circuit model of the Boolean function. The proposed models are empirical in nature. The model estimates area within 6% error and 12% error of synthesized results obtained with SIS and a commercial tool. The power estimation model predicts power within 15% error of synthesized results obtained with a commercial tool. We further show that the technique is quite robust to change in technology as well. Our technique depends on training on random circuits with very few inputs (4 to 6 inputs) and we show that the size of the training set is rather small ( 400) to achieve the errors reported.