Lab Details

PACE Lab : Programming Languages, Architecture, Compilers Education LaboratoryLink to Lab Webpage

Research Areas	Memory System Design, Network-on-chip architectures, Cache Design in Multicore, Program Analysis, Parallelization, Code Optimization.
Members	Faculty : Madhu Mutyam, V. Krishna Nandivada, Rupesh Nasre. Students/Scholars : . PhD : Praveen Kumar Alapati, Raghesh A, Gnaneswara Rao J, Aman Nougrahiya, Jyothi Krishna V S, Manas Thakur, Venkata Naga Jyothi V, Saurabh Mohanrao Kalikar, Chongala .S.R.Swamy Saranam, Somesh Singh, Somesh Singh, Shouvick Mondal, Anju M A. MS : Nizamudheen Ahmed, Shashidhar G, Rakesh Patil, Rahul Shrivastava, Dennis Antony Varkey, Anchu R S, Aman Sharma, Sayantan Ray, Puneet Saraf, Arun T, Joe Augustine, Rajendra Kumar Dangwal, Diptanshu Kakwani. M.Tech : Manoj Gangadhar Dongare, Akshay M Potey, Abhishek Chakraborty, Himanshu Gaur, Preetam Kumar Ghosh, Ajay Sharma, Tejas Wangikar, Gaurav Arora, Atul Dhiman, Shahbaz Husain, Bokka Pradeep, Kamat Shantanu Sunil, Ankur Yadav. B.Tech(DD) : Akshay Utture, Sistla Meghana Aparna, Bikash Gogoi. Project Staffs :
Recent Publications	QADroid: regression event selection for Android applications. Aman Sharma , Rupesh Nasre Appeared in Proceedings of the 28th ACM SIGSOFT International Symposium on Software Testing and Analysis, ISSTA 2019, Beijing, China, July 15-19, 2019., pp.66-77, Jul 2019 Optimizing graph processing on GPUs using approximate computing: poster. Somesh Singh , Rupesh Nasre Appeared in Proceedings of the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2019, Washington, DC, USA, February 16-20, 2019, pp.395-396, Feb 2019 Compare less, defer more: scaling value-contexts based whole-program heap analyses. Manas Thakur , V. Krishna Nandivada Appeared in Proceedings of the 28th International Conference on Compiler Construction, CC 2019, Washington, DC, USA, February 16-17, 2019, pp.135-146, Feb 2019 Efficiency and expressiveness in UW-OpenMP. Raghesh A , V. Krishna Nandivada Appeared in Proceedings of the 28th International Conference on Compiler Construction, CC 2019, Washington, DC, USA, February 16-17, 2019, pp.182-192, Feb 2019 Formal Modeling and Verification of a Victim DRAM Cache. Debiprasanna Sahoo , Swaraj Sha , Manoranjan Satpathy , Madhu Mutyam , S. Ramesh , Partha S. Roop Appeared in ACM Trans. Design Autom. Electr. Syst., Vol 24, pp.20:1-20:23, Jan 2019
Sponsored Projects	Dynamic Graph Algorithms on Manycores (Funding Agency :IITM-ERP) Formal Verification and Synthesis of Secure Designs. (Funding Agency :NFSG) Exploring Techniques to Optimize Main Memory of Multi-Core Systems (Funding Agency :DST) IBM Shared University Research Grant (Funding Agency :IBM-SURG) Research funding from Board of Research in Nuclear Sciences (Funding Agency :DAE)

Department of Computer Science & Engineering

Indian Institute of Technology Madras, Chennai, India.