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Undergraduate Core

CS2300: Foundations of Computer Systems Design

This course helps students design and implement a simple but functional processor microarchitecture from first principles. It moves from digital logic and combinational design to sequential systems, stored-program execution, instruction-set design, and a complete working CPU implementation.

CS2300 course image
Latest Offering Diwali'26 (July - Nov, 2026)
Instructor Ayon Chakraborty
Materials Moodle GATE Questions
Focus Digital design to microarchitecture

The course is divided into two broad components: digital design and processor design. Students first learn logic-related fundamentals and core circuit-design skills, then connect stored-program execution to instruction-set architecture, machine code, and a hardware platform capable of storing and executing code.

The accompanying video playlist is based on the online IIT Madras BS Data Science systems-bucket offering. The classroom version is positioned to help students transition smoothly into CS2600 and later CS6600 by first learning how to build a correct computer before worrying about performance and then state-of-the-art architectural optimization.

The playlist follows the online IIT Madras BS Data Science version of the course and works as a companion to the in-class material hosted on Moodle. Please note that the version offered as a part of BS Data Science is significantly diluted in terms of rigour compared to the version I offer for our B.Tech program.

Syllabus and TARA16 Lab

TARA16
Course Materials
TARA16-Book
GATE Questions

To the Students

You have written programs. You may even have written many. Somewhere along the way, you have probably wondered what actually happens when a program runs. Perhaps the thought came only briefly before you returned to an assignment due at midnight. Not the folklore answer that a compiler turns it into ones and zeros. This course goes deeper. It asks what physical arrangement of parts takes a statement such as x = a + b; and makes it true.

Most curricula answer this question in two halves that never quite meet. A digital design course teaches gates, Karnaugh maps, registers, counters, and perhaps finite state machines. Then it stops. A computer architecture course starts with an assembled processor and asks how to make it faster. This course bridges this crucial gap.

How do a few thousand gates and flip-flops become a machine that runs a program?

The promise of no black boxes

This course makes one promise. Nothing will be hidden from you. Every box we draw gets opened. A register becomes flip-flops with a load enable. A flip-flop becomes two latches. A latch becomes two crossed gates. A gate becomes transistors, if you care to look. By the final module, you will have specified and verified every component of the processor using parts you already trust.

That processor is TARA16, a complete 16-bit computer with eight registers, a clean instruction set, memory-mapped I/O, and a display you can draw to. It is small enough to hold in your head and honest enough to build. It is not a toy. It runs real programs, including sorting, recursion, and games. It also exists as a real machine in three forms you can touch. The TARA16 Studio simulator lets you write and run TARA16 assembly from the first week and watch every register change. You can build and probe a gate-level version in a circuit simulator. A Verilog implementation runs on an FPGA board, where the machine you studied on paper draws to an actual screen. All three agree with one another, instruction for instruction. The final module shows you how that agreement is checked. Knowing why you believe a design is correct is part of the design.

One more thing. Hardware design has a reputation for being arcane, the province of a few. It is not. A processor is a finite, knowable object, built from a handful of ideas used honestly and repeatedly. By the end of this course, you will not merely know how a computer works. You will have designed one, and you will know why it is designed the way it is. That knowledge does not expire with any particular technology. It is yours to keep.

Welcome. Let us build a computer.

Module 1 Foundations: From Software to Digital Hardware Click to expand

Module Topics

  • The Computing Stack: Computability, abstraction layers, source code, assembly, machine code, memory, and stored-program execution.
  • The TARA16 Machine Model: Programmer-visible state: PC, IR, registers, memory, condition flags, and the ISA as a behavioral contract.
  • TARA16 Assembly Programming: Arithmetic, logic, loads, stores, branches, loops, labels, and flag-driven control flow.
  • Register Transfer Language: RTL notation, fetch-decode-execute sequences, and the bridge from instruction behavior to datapath hardware.
Module 2 Data, Bits, and Logic Click to expand

Module Topics

  • Data Representation: Bit patterns, bytes, words, hexadecimal notation, digital abstraction, and endian-aware interpretation.
  • Number Representation: Unsigned integers, base conversion, signed magnitude, one's complement, two's complement, shifts, and overflow.
  • Boolean Logic: Bitwise operations, masks, Boolean algebra, De Morgan's laws, truth tables, SOP/POS, NAND/NOR realization.
  • CMOS Enrichment: Transistors as switches, CMOS gates, propagation delay, fan-out, and static/dynamic power.
Module 3 Combinational Logic and the TARA16 ALU Click to expand

Module Topics

  • Combinational Model: Output-as-function, timing specifications, critical paths, glitches, and hazard-aware design.
  • Logic Simplification: Canonical forms, Karnaugh maps, don't-cares, multi-level logic, and bubble pushing.
  • Building Blocks: Muxes, demuxes, decoders, encoders, comparators, wide logic, and their datapath/control uses.
  • TARA16 ALU: Adders, subtraction, carry lookahead, operation selection, flag generation, and PLA-style control logic.
Module 4 Sequential Logic, Memory, and Control Click to expand

Module Topics

  • Time and Clocking: Why state is needed, setup/hold constraints, clock period, and synchronous design discipline.
  • Latches and Flip-Flops: SR latches, gated D latches, edge-triggered D flip-flops, JK/T flip-flops, and excitation tables.
  • Storage Blocks: Enabled registers, register files, buses, shift registers, counters, ROM, RAM, MAR, MDR, and IR.
  • FSM Control: Moore/Mealy machines, ASM charts, sequence detectors, and counter-controlled datapaths.
Module 5 TARA16 Microarchitecture Design and Implementation Click to expand

Module Topics

  • ISA-Microarchitecture Contract: Architectural correctness, single-cycle versus multicycle design, and preserving observable state.
  • TARA16 Datapath: PC, IR, register file, MAR/MDR, ALU result paths, bus organization, and mux-controlled data movement.
  • Instruction Cycle: Common fetch RTL, execute sequences by instruction class, and disciplined control-signal derivation.
  • Control and Validation: T-state counters, hardwired control, microprogramming, FSM controllers, block tests, traces, and program demos.

A game running on the VGA display, live keyboard control, and memory being debugged from TARA16 Studio.

TARA16 ISA summary
Format Instructions Encoding layout
F0 NOP, HLT, RET op[15:11] 00000000000
F1 ADD, SUB, MUL, AND, OR, XOR, SLT op rd rsA rsB 00
F2 MOV, NOT op rd rs 00000
F3 LIL, LIH, ADDI, SHL, SHR op rd imm8
F4 LDW, STW, LDB, STB op rdata rbase off5
F5 BZ, BN op rtest rel8
F6 JMP, CALL op rel11
F7 PUSH, POP op rstk 00000000

Course document

Books

Extra References

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