Practice questions from past GATE papers

A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)? [GATE CSE 2006]

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is [GATE CSE 2007]

(Common data with Question 2.) Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is [GATE CSE 2007]

Which of the following is/are true of the auto-increment addressing mode?

[GATE CSE 2008]

Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory? [GATE CSE 2011]

Consider the following sequence of micro-operations.

Which one of the following is a possible operation performed by this sequence? [GATE CSE 2013]

A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ________. [GATE CSE 2014]

For computer based on three-address instruction formats, each address field can be used to specify which of the following:

[GATE CSE 2015]

A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least ________ bits. [GATE CSE 2016]

A processor has 40 distinct instruction and 24 general purpose registers. A 32-bit instruction word has an opcode, two registers operands and an immediate operand. The number of bits available for the immediate operand field is ________. [GATE CSE 2016]

Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is ________. [GATE CSE 2016]

Consider the C struct defined below:

The base address of student is available in register R1. The field student.grade can be accessed efficiently using: [GATE CSE 2017]

Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence

If the target of the branch instruction is $i$, then the decimal value of the Offset is ________. [GATE CSE 2017]

A processor has 16 integer registers (R0, R1, …, R15) and 64 floating point registers (F0, F1, …, F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3, and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of $N$ instructions, each with a floating point register operand (1F). The maximum value of $N$ is ________. [GATE CSE 2018]

Consider the following data path diagram.

[GATE CSE 2020]

Consider an instruction: R0 $\leftarrow$ R1 $+$ R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts $r$ and $w$ indicate read and write operations, respectively.

Which one of the following is the correct order of execution of the above steps?

A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is ________. [GATE CSE 2020]

Consider the following instruction sequence where registers R1, R2 and R3 are general purpose and MEMORY$[X]$ denotes the content at the memory location $X$.

Assume that the content of the memory location 5000 is 10, and the content of the register R3 is 3000. The content of each of the memory locations from 3000 to 3020 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location 3010 is ________. [GATE CSE 2021]

Consider the given C-code and its corresponding assembly code, with a few operands $U_1$--$U_4$ being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable. [GATE CSE 2023]

Which one of the following options is a CORRECT replacement for operands in the position $(U_1, U_2, U_3, U_4)$ in the above assembly code?

A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is ________ [GATE CSE 2024]

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.

R-type Instruction Format:

I-type Instruction Format:

In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size. Let $X$ be the number of bits used to encode the UNUSED field, $Y$ be the number of bits used to encode the OPCODE field, and $Z$ be the number of bits used to encode the immediate value/address field. The value of $X + 2Y + Z$ is ________ [GATE CSE 2024]

A machine has a 32-bit architecture with 1-word long instructions. It has 24 registers and supports an instruction set of size 40. Each instruction has five distinct fields, namely opcode, two source register identifiers, one destination register identifier, and an immediate value. Assuming that the immediate operand is an unsigned integer, its maximum value is ________. [GATE ECE 2024]

A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown? [GATE CSE 2025]

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?

[GATE CSE 2025]

Which of the following is/are part of an Instruction Set Architecture of a processor? [GATE CSE 2025]

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand. Which one of the following sequences of instructions corresponds to the high-level language statement $Z = X + Y$?

Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers. [GATE CSE 2026]

Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has 2 register operands and a 6-bit immediate operand. Each R-type instruction has 3 register operands. Each C-type instruction has a register operand and a 6-bit offset value. If there are 2 unique M-type opcodes and 7 unique R-type opcodes, which one of the following options gives the maximum number of unique opcodes possible for C-type instructions? [GATE CSE 2026]

We consider the addition of two $2's$ complement numbers $b_{n-1}b_{n-2}\dots b_{0}$ and $a_{n-1}a_{n-2}\dots a_{0}$. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by $c_{n-1}c_{n-2}\dots c_{0}$ and the carry-out by $c_{out}$. Which one of the following options correctly identifies the overflow condition? [GATE CSE 2006]

$X=01110$ and $Y=11001$ are two 5-bit binary numbers represented in two's complement format. The sum of $X$ and $Y$ represented in two's complement format using 6 bits is [GATE ECE 2007]

Let $r$ denote number system radix. The only value(s) of $r$ that satisfy the equation $\sqrt{121_r}={11}_r$ is/are [GATE CSE 2008]

The two numbers represented in signed 2's complement form are $P=11101101$ and $Q=11100110$. If $Q$ is subtracted from $P$, the value obtained in signed 2's complement form is [GATE ECE 2008]

$(1217)_8$ is equivalent to [GATE CSE 2009]

$P$ is a $16$-bit signed integer. The $2$'s complement representation of $P$ is $(F87B)_{16}$. The $2$'s complement representation of $8\times P$ is [GATE CSE 2010]

The smallest integer that can be represented by an $8\text{-bit}$ number in $2's$ complement form is [GATE CSE 2013]

The base (or radix) of the number system such that the following equation holds is________.

$\frac{312}{20} = 13.1$ [GATE CSE 2014, Set 1]

Consider the equation $(123)_5=(x8)_y$ with $x$ and $y$ as unknown. The number of possible solutions is ________ . [GATE CSE 2014, Set 2]

Consider the function func shown below:

int func(int num)
{
    int count = 0;
    while (num)
    {
        count++;
        num >>= 1;
    }
    return (count);
}

The value returned by func(435) is ________. [GATE CSE 2014, Set 2]

The number of bytes required to represent the decimal number 1856357 in packed BCD (Binary Coded Decimal) form is ________ . [GATE ECE 2014, Set 2]

The $16\text{-bit}\;2's$ complement representation of an integer is $1111 \quad 1111 \quad 1111 \quad 0101;$ its decimal representation is ________ [GATE CSE 2016, Set 1]

Let $X$ be the number of distinct $16$-bit integers in $2's$ complement representation. Let $Y$ be the number of distinct $16$-bit integers in sign magnitude representation Then $X - Y$ is________. [GATE CSE 2016, Set 2]

When two $8\text{-bit}$ numbers $A_{7}\cdots A_{0}$ and $B_{7}\cdots B_{0}$ in $2$'s complement representation (with $A_{0}$ and $B_{0}$ as the least significant bits) are added using a ripple-carry adder, the sum bits obtained are $S_{7}\cdots S_{0}$ and the carry bits are $C_{7}\cdots C_{0}$. An overflow is said to have occurred if [GATE CSE 2017, Set 1]

(A) the carry bit $C_{7}$ is $1$

(B) all the carry bits $\left ( C_{7},\cdots ,C_{0} \right )$ are $1$

(C) $\left ( A_{7} \cdot B_{7} \cdot \overline{S_{7}}+\overline{A_{7}} \cdot \overline{B_{7}} \cdot S_{7} \right )$ is $1$

(D) $\left ( A_{0} \cdot B_{0} \cdot \overline{S_{0}}+\overline{A_{0}} \cdot \overline{B_{0}} \cdot S_{0} \right )$ is $1$

The representation of the value of a $16\text{-bit}$ unsigned integer $X$ in hexadecimal number system is $\textsf{BCA9}$. The representation of the value of $X$ in octal number system is [GATE CSE 2017, Set 2]

Consider a quadratic equation $x^2-13x+36=0$ with coefficients in a base $b$. The solutions of this equation in the same base $b$ are $x=5$ and $x=6$. Then $b=$ ________. [GATE CSE 2017, Set 2]

In $16$-bit $2$'s complement representation, the decimal number $-28$ is: [GATE CSE 2019]

Consider $Z=X-Y$ where $X, Y$ and Z are all in sign-magnitude form. X and Y are each represented in $n$ bits. To avoid overflow, the representation of $Z$ would require a minimum of: [GATE CSE 2019]

$P$, $Q$, and $R$ are the decimal integers corresponding to the 4-bit binary number 1100 considered in signed magnitude, 1's complement, and 2's complement representations, respectively. The 6-bit 2's complement representation of $(P+Q+R)$ is [GATE ECE 2020]

Let the representation of a number in base $3$ be $210$. What is the hexadecimal representation of the number? [GATE CSE 2021, Set 1]

Let $\text{R1}$ and $\text{R2}$ be two $4 - \text{bit}$ registers that store numbers in $2\text{'s}$ complement form. For the operation $\text{R1 + R2},$ which one of the following values of $\text{R1}$ and $\text{R2}$ gives an arithmetic overflow? [GATE CSE 2022]

Consider a system that uses $5$ bits for representing signed integers in $2$ 's complement format. In this system, two integers $A$ and $B$ are represented as $A$=$01010$ and $B$=$11010$. Which one of the following operations will result in either an arithmetic overflow or an arithmetic underflow? [GATE CSE 2024, Set 1]

In a number system of base $r$, the equation $x^2-12x+37=0$ has $x=8$ as one of its solutions. The value of $r$ is ________. [GATE ECE 2024]

The number $-6$ can be represented as $1010$ in $4$-bit $2$'s complement representation. Which of the following is/are CORRECT $2$ 's complement representation(s) of $-6$? [GATE CSE 2025, Set 1]

Consider the 8-bit signed integers $X$, $Y$ and $Z$ represented using the sign-magnitude form. The binary representations of $X$ and $Y$ are as follows:

Which of the following operations to compute $Z$ result(s) in an arithmetic overflow? [GATE CSE 2026, Set 1]

In a system, numbers are represented using 4-bit two's complement form. Consider four numbers $N_1=1011$, $N_2=1101$, $N_3=1010$ and $N_4=1001$ in the system. Which of the following operations will result in arithmetic overflow? [GATE CSE 2026, Set 2]

What is the 10's complement of $(47)_{10}$? [GATE ECE 2026]

The $2$'s complement representation of the decimal value $-15$ is [GATE CSE 2002]

Zero has two representations in [GATE CSE 1999]

The number $43$ in $2's$ complement representation is [GATE CSE 2000]

The $2$'s complement representation of $(-539)_{10}$ in hexadecimal is [GATE CSE 2001]

The decimal value $0.25$ [GATE CSE 2002]

The range of integers that can be represented by an $n$ bit $2's$ complement number system is: [GATE CSE 2005]

A logical binary relation $\Box$, is defined as follows:

Let $\sim$ be the unary negation (NOT) operator, with higher precedence than $\Box$.

Which one of the following is equivalent to $A\land B$? [GATE CSE 2006]

Consider the circuit above. Which one of the following options correctly represents $f\left(x,y,z\right)$ [GATE CSE 2006]

Given two three bit numbers $a_{2}a_{1}a_{0}$ and $b_{2}b_{1}b_{0}$ and $c$ the carry in, the function that represents the carry generate function when these two numbers are added is: [GATE CSE 2006]

(A) $a_{2}b_{2}+a_{2}a_{1}b_{1}+a_{2}a_{1}a_{0}b_{0}+a_{2}a_{0}b_{1}b_{0}+a_{1}b_{2}b_{1}+a_{1}a_{0}b_{2}b_{0}+a_{0}b_{2}b_{1}b_{0}$

(B) $a_{2}b_{2}+a_{2}b_{1}b_{0}+a_{2}a_{1}b_{1}b_{0}+a_{1}a_{0}b_{2}b_{1}+a_{1}a_{0}b_{2}+a_{1}a_{0}b_{2}b_{0}+a_{2}a_{0}b_{1}b_{0}$

(C) $a_{2}+b_{2}+(a_{2}\oplus b_{2}) ( a_{1}+b_{1}+(a_{1}\oplus b_{1})+(a_{0}+b_{0}))$

(D) $a_{2}b_{2}+\overline{a_{2}}a_{1}b_{1}+\overline{a_{2}a_{1}}a_{0}b_{0}+\overline{a_{2}}a_{0}\overline{b_{1}}b_{0}+a_{1}\overline{b_{2}}b_{1}+\overline{a_{1}}a_{0}\overline{b_{2}}b_{0}+a_{0}\overline{b_{2}b_{1}}b_{0}$

Consider a Boolean function $f(w,x,y,z)$. Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors $i_{1}=\left \langle w_{1}, x_{1}, y_{1},z_{1}\right \rangle$ and $i_{2}=\left \langle w_{2}, x_{2}, y_{2},z_{2}\right \rangle$ , we would like the function to remain true as the input changes from $i_{1}$ to $i_{2}$ ($i_{1}$ and $i_{2}$ differ in exactly one bit position) without becoming false momentarily.

Let $f(w,x,y,z)=\sum (5,7,11,12,13,15)$ . Which of the following cube covers of $f$ will ensure that the required property is satisfied? [GATE CSE 2006]

What is the maximum number of different Boolean functions involving $n$ Boolean variables? [GATE CSE 2007]

How many $3$-to-$8$ line decoders with an enable input are needed to construct a $6$-to-$64$ line decoder without using any other logic gates? [GATE CSE 2007]

Consider the following Boolean function of four variables:

The function is [GATE CSE 2007]

Let $f(w, x, y, z) = \sum {\left(0,4,5,7,8,9,13,15\right)}$. Which of the following expressions are NOT equivalent to $f$?

P: $x'y'z' + w'xy' + wy'z + xz$

Q: $w'y'z' + wx'y' + xz$

R: $w'y'z' + wx'y' + xyz+xy'z$

S: $x'y'z' + wx'y'+ w'y$ [GATE CSE 2007]

Define the connective $*$ for the Boolean variables $X$ and $Y$ as:

Let $Z = X * Y$. Consider the following expressions $P$, $Q$ and $R$.

Which of the following is TRUE? [GATE CSE 2007]

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer needed? [GATE CSE 2007]

In a look-ahead carry generator, the carry generate function $G_i$ and the carry propagate function $P_i$ for inputs $A_i$ and $B_i$ are given by:

The expressions for the sum bit $S_i$ and the carry bit $C_{i+1}$ of the look ahead carry adder are given by:

Consider a two-level logic implementation of the look-ahead carry generator. Assume that all $P_i$ and $G_i$ are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a $4$-bit adder with $S_3, S_2, S_1, S_0$ and $C_4$ as its outputs are respectively: [GATE CSE 2007]

The Boolean function $Y=AB+CD$ is to be realized using only 2-input NAND gates. The minimum number of gates required is [GATE ECE 2007]

The Boolean expression $Y=\bar A\bar B\bar C D+\bar A B C\bar D+A\bar B\bar C D+AB\bar C\bar D$ can be minimized to [GATE ECE 2007]

In the following circuit, $X$ is given by

[GATE ECE 2007]

In the Karnaugh map shown below, $X$ denotes a don't care term. What is the minimal form of the function represented by the Karnaugh map?

[GATE CSE 2008]

If $P, Q, R$ are Boolean variables, then

$(P + \bar{Q}) (P.\bar{Q} + P.R) (\bar{P}.\bar{R} + \bar{Q})$ simplifies to [GATE CSE 2008]

The logic function implemented by the following circuit at the terminal OUT is

[GATE ECE 2008]

Which of the following Boolean Expressions correctly represents the relation between $P$, $Q$, $R$ and $M_1$?

[GATE ECE 2008]

For the circuit shown in the following figure, $I_0$-$I_3$ are inputs to the $4:1$ multiplexer. $R$ (MSB) and $S$ are control bits.

The output $Z$ can be represented by [GATE ECE 2008]

What is the minimum number of gates required to implement the Boolean function $\text{(AB+C)}$ if we have to use only $2\text{-input NOR}$ gates? [GATE CSE 2009]

The binary operation $\Box$ is defined as follows

Which one of the following is equivalent to $P\lor Q$? [GATE CSE 2009]

If $X=1$ in the logic equation $[X+Z\{\bar Y+(\bar Z+X\bar Y)\}]\{\bar X+\bar Z(X+Y)\}=1$, then [GATE ECE 2009]

What are the minimum number of 2-to-1 multiplexers required to generate a 2-input AND gate and a 2-input Ex-OR gate ? [GATE ECE 2009]

Statement for Linked Answer Questions 59 and 60.

Two products are sold from a vending machine, which has two push buttons $P_1$ and $P_2$. When a button is pressed, the price of the corresponding product is displayed in a 7-segment display.

• If no buttons are pressed, ‘0' is displayed, signifying ‘Rs. 0'.
• If only $P_1$ is pressed, ‘2' is displayed, signifying ‘Rs. 2'.
• If only $P_2$ is pressed, ‘5' is displayed, signifying ‘Rs. 5'.
• If both $P_1$ and $P_2$ are pressed, ‘E' is displayed, signifying ‘Error'.

The names of the segments in the 7-segment display, and the glow of display for ‘0', ‘2', ‘5' and ‘E', are shown below.

Consider

(i) push button pressed/not pressed is equivalent to logic 1/0 respectively,

(ii) a segment glowing / not glowing in the display is equivalent to logic 1/0 respectively.

If segments $a$ to $g$ are considered as functions of $P_1$ and $P_2$, then which of the following is correct ? [GATE ECE 2009]