CS6600: Computer Architecture (3-1-0-0-8-12-12)

Objective:

The course provides detailed discussion on architectural mechanisms, which exploit parallelism available in programs at various granularities, and programming tools to work with such architectures.

Syllabus:

Introduction: Defining computer architecture, Flynn's classification of computers, Metrics for performance measurement, Instruction set architecture.
Memory Hierarchy: Introduction, Advanced optimizations of cache performance, Memory technology and optimizations, Virtual memory and virtual machines, The design of memory hierarchy, Case study -- Memory hierarchies in latest CPUs.
Instruction Level Parallelism: Concepts and Challenges, Basic compiler techniques for exposing ILP, Reducing branch costs and advanced branch prediction, Dynamic scheduling, Advanced techniques for instruction delivery and speculation, Limitations of ILP, Multithreading: Exploiting thread-level paralleism to improve uniprocessor throughput, Case study -- Dynamic scheduling in latest CPUs.
Thread Level Parallelism: Introduction, Shared memory multicore systems, Performance metrics for shared-memory multicore systems, Cache coherence protocols, Memory consistency, Synchronization, Network-on-Chip, Case study -- thread level parallelism in latest CPUs.
Data Level Parallelism: Introduction, Vector architecture, SIMD instruction set extensions for multimedia, Graphics processing units, GPU memory hierarchy, Detecting and enhancing loop-level parallelism, Case study -- Data level parallelism in latest GPUs.

Text Book:

J.L. Hennessy and D.A. Patterson. Computer Architecture: A Quantitative Approach. 6th Edition, Morgan Kauffmann Publishers, 2017.

Reference Books/Material:

J.P. Shen and M.H. Lipasti. Modern Processor Design: Fundamentals of Superscalar Processors. McGraw-Hill Publishers, 2005.
V. Nagarajan, D.J. Sorin, M.D. Hill, and D.A. Wood. A Primer on Memory Consistency and Cache Coherence. 2nd Edition, Morgan & Claypool, 2020.
N.E. Jerger and L.S. Peh. On-Chip Networks. Morgan & Claypool, 2009.

Evaluation Mechanism:

Lecture Venue and Schedule: CS26 and H Slot (Mon-14:00-15:15; Tue-15:30-16:45; Thu-17:00-17:50)

Last modified: Jul 17th, 2025.