SIGNED: A Challenge-Response Scheme for Electronic Hardware Watermarking (IEEE TComp, 2022) [link]
A Formal Analysis of Prefetching in Profiled Cache-Timing Attacks on Block Ciphers (Journal of Cryptology, 2021) [link]
PERI: a Posit enabled RISC-V core (ACM TACO, 2021) [link]
FEDS: Comprehensive Fault Attack Exploitability Detection for Software Implementations of Block Ciphers (IACR TCHES, 2020) [link]
BRUTUS: Refuting the Security Claims of the Cache Timing Randomization Countermeasure proposed in CEASER (IEEE Computer Architecture Letters, 2020) [link]
Conferences
Anchors that Dont Lift: Understanding Supply Chain Driven
Kernel Lock-In and Governance-Mediated Mitigation Strategies in SOHO (Usenix Security 2026)
WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors (USENIX Security, 2024) [link] (Distinguished Paper Award)
Kryptonite: Worst-Case Program Interference Estimation on Multi-Core Embedded Systems (EMSOFT, 2023) [link]
Timed Speculative Attacks exploiting Store to Load Forwarding bypassing Cache-based Countermeasures[link] (DAC, 2022)
PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance (IEEE HOST, 2020) [link] (Best Paper Award)
SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware (DATE, 2020) [link]
Karna: A Gate-Sizing based Security aware EDA Flow for Improved Power Side-Channel Attack Protection (ICCAD 2019) [link]