Speaker: Dr. Nikita Yadav (Microsoft)

Date: Mar 13, 2026

Time: 11:00 AM

Venue: MR1 (SSB 233, First Floor)

Abstract:

Control-Flow Attestation (CFA) is a technique for verifying the integrity of program execution by attesting to its control-flow path. It is particularly useful for auditing execution, allowing one to prove that a program ran as expected or to perform a post-mortem analysis when execution deviates from expected behaviour. Since its introduction in 2016, CFA has primarily been applied in the embedded systems domain. CFA techniques work by instrumenting the prover program to collect runtime control-flow path measurements, which are committed to a Trusted Execution Environment (TEE), such as the secure world of an ARM TrustZone-enabled processor. These measurements are signed by the TEE and later verified by a trusted verifier, who checks whether the program followed the expected path for a given input. However, two key challenges hinder the practical deployment of CFA: (1) scaling to whole-program execution, and (2) supporting complex environments beyond bare-metal systems, i.e., non-bare-metal settings where the prover program runs atop an operating system (OS). In this talk, we will discuss approaches to address these limitations by answering two key questions: (1) What causes the high runtime overhead in existing CFA systems, and how can it be reduced? (2) How can CFA be made secure in non-bare-metal settings where the OS-level adversaries may compromise the system?

Speakr Bio:
Nikita Yadav is a Postdoctoral Researcher in the Future of Scalable Software Engineering group at Microsoft. Prior to this, she completed her PhD at the Indian Institute of Science (IISc), Bangalore, where she worked with Prof. Vinod Ganapathy on problems related to computer systems, with a focus on security, trusted hardware, and proof-of-execution protocols. She previously earned her bachelor’s degree in CSE from the National Institute of Technology (NIT), Kurukshetra and her master’s degree from IISc. She was awarded PMRF in May 2021, and her research projects have spanned diverse domains, including blockchain, decentralized networks, and embedded systems. Her work has been published in top-tier security conferences, including ACM CCS, NDSS and USENIX Security. In 2024, she received the Google PhD Fellowship and was honoured with the 'Murthy Govindaraju Women in Computer Science Research Endowment Award' at IISc.

Speaker: Mr. Vipin Bharathan

Date: Mar 12, 2026

Time: 05:00 PM

Venue: SSB 334 (A M Turing Hall)

Abstract:

The session will cover topics such as:
Post-Quantum Cryptography (PQC) and Crypto
Stablecoins
DeFi and Traditional Finance
CBDC adoption across China, India, and the Euro Zone
Blockchain outlook and trends for 2026

Speaker Bio:
Vipin Bharathan (1982 B.Tech and 1984 M.Tech, IIT Madras) is a thought leader in Web3 and emerging technologies and the founder of dlt.nyc, a consulting practice focused on distributed ledger technology, capital markets, tokenization, and regulation. He is a Forbes contributor on blockchain and digital assets and actively participates in the Hyperledger community as Chair of the Capital Markets Special Interest Group and the Identity Working Group. He has contributed to the Token Taxonomy Framework, defining key token attributes, and authored a paper proposing a novel architecture for Central Bank Digital Currencies (CBDCs). With extensive experience as a developer, development manager, product owner, and technical strategist in financial systems, he has worked with numerous programming languages from Algol and COBOL to Python, Rust, and Go. He also helped build the open-source CBDC prototype “eThaler” in Hyperledger Labs, later adapted into a carbon token and demonstrated to global institutions such as the IMF and the World Bank.

Speaker: Yamini Shankar (CS22D002)

Date: Mar 11, 2026

Time: 11:00 AM

Venue: SSB 134 (Ground Floor)

Abstract:

Radio Frequency (RF)-based sensing provides a privacy-preserving and non-intrusive alternative to vision-based systems for applications such as human activity recognition, indoor monitoring, and environmental sensing. Recent advances in WiFi sensing enable IoT devices to extract fine-grained physical layer measurements: Channel State Information (CSI), and apply machine learning techniques for perception tasks. However, scaling such sensing systems introduces a critical challenge: the continuous transmission of high-dimensional CSI data from multiple distributed sensors can overwhelm network resources, leading to congestion, increased latency, and degraded performance for regular network traffic.
To address this challenge, we propose AutoCompress, a model-aware framework designed to reduce the network overhead of distributed RF sensing systems. The key idea is to intelligently select only the most informative time-frequency components of CSI spectrograms prior to transmission. AutoCompress leverages a sparsity based technique to compute importance scores that identify the most relevant elements for inferencing. These scores guide a bandwidth-aware sensor-subcarrier selection strategy enabling significant compression of sensing data while maintaining inference accuracy.
AutoCompress is evaluated using the UT-HAR dataset and a real-world Nexmon-based WiFi sensing testbed. The results show that AutoCompress achieves over 4000× reduction in CSI data transmission, improves network throughput by 35.5%, and reduces sensing latency by more than 90%, while preserving sensing accuracy.

Speaker: Soumen Pachal (CS22D009)

Date: Mar 11, 2026

Time: 10:00 AM

Venue: Paanini Meeting Room (MR 2, CSB 21 First Floor)

Abstract:

In this talk, we discuss a family of generalized Hessian estimators of the objective using random direction stochastic approximation (RDSA) by utilizing only noisy function measurements. The form of each estimator and the order of the bias depend on the number of function measurements. In particular, we demonstrate that estimators with more function measurements exhibit lower-order estimation bias. We show the asymptotic unbiasedness of the estimators. We also perform asymptotic and non-asymptotic convergence analyses for stochastic Newton methods that incorporate our generalized Hessian estimators. Finally, we perform numerical experiments to validate our theoretical findings.

Speaker: Prof. Shweta Agrawal

Date: Mar 09, 2026

Time: 03:30 PM

Venue: SSB 134

Abstract:

Cryptography is a beautiful branch of theoretical computer science that seeks to provide guarantees to the art of secret keeping. The questions it poses are fundamental -- does the universe permit asymmetry of computation? Its practical utility requires no argument -- ad-hoc security solutions repeatedly fall prey to attack and crime is increasingly digital. Its scientific charm lies in its deeply paradoxical nature, in its uncanny ability to enable what should really not be possible.


In this talk, we'll take a peek at some of the surprising constructs of cryptography and get a taste of how to walk the tightrope between mathematical structure and computational hardness. We'll see how different mathematical structures have different personalities and will cooperate for some tasks while stubbornly refusing to budge on others. We'll try to approach the exciting, and not always happy, relationship of cryptography with quantum computing.

No background in cryptography will be assumed.

Speaker Bio: Shweta Agrawal is a professor and the Venky Harinarayan and Anand Rajaraman Faculty Fellow at the Department of Computer Science and Engineering at IIT Madras. She works in the area of cryptography, with a focus on post-quantum cryptography. Her work has received over 5000 citations and has appeared at flagship venues in cryptography. She has won multiple awards and honours such as the Rashtriya Vigyan Puraskar (Shanti Swarup Bhatnagar award), Swarnajayanti award, the ACM India award for Outstanding Contributions to Computing by a Woman, a best paper award at flagship conference Eurocrypt, Google India faculty award, BY award for excellence in research and teaching and best reviewer awards at CCS, Eurocrypt, Asiacrypt. She has been an invited speaker at prestigious global conferences like Asiacrypt and “Women in Mathematics”, served as program co-chair for the flagship conference Asiacrypt and serves as associate editor for the "SIAM Journal of Computing", "Journal of Cryptology" and "Information and Computation".
============================

Speaker: Vipul Harsh

Date: Mar 06, 2026

Time: 10:00 AM

Venue: SSB 334 (A M Turing Hall)

Abstract:

Modern Internet-scale services must identify and mitigate customer-impacting incidents quickly. Despite the development of many Root Cause Analysis (RCA) algorithms—including recent LLM-assisted solutions—existing approaches struggle with the "long tail" of novel failure modes and the sheer scale of telemetry. In this talk, I argue that the path forward requires a paradigm shift from developing point-solution algorithms to a systems-first approach. I will introduce MoCE: a Mixture-of-Experts (MoE) framework that provides high-level abstractions for failure diagnosis. This framework enables developers to express complex troubleshooting logic succinctly using MoCE’s domain specific operators while providing the underlying systems support for scalable telemetry processing. Finally, I will briefly describe how these abstractions empower reliable, autonomous agents to perform interactive diagnosis and discuss ongoing and promising future work based on these ideas.

Speaker: Amitabh Trehan (Durham University)

Date: Mar 03, 2026

Time: 02:00 PM

Venue: SSB 334 (A M Turing Hall)

Abstract:

In the field of distributed algorithm design, it is often standard to abstract the network as an undirected graph with the nodes as vertices and connections as edges. About the simplest process one can imagine on a network/graph is flooding: A node is in possession of a message M which has to be eventually sent to every node on the graph (this is called achieving broadcast)- the node sends M immediately to all its neighbours and they send to all their neighbours they did not just receive the message from and so on. Clearly, this achieves broadcast. But, how to achieve termination? i.e. the copies of the message should not circulate indefinitely.

At the advent of distributed computing, more than 50 years ago, a simple solution was devised - keep a copy of M, and if M is received again, simply discard this M. However, this requires memory/state and a stack of earlier received messages. Surprisingly, we discovered [PODC2019,STACS2020,DC2023] that state is unnecessary to achieve terminating broadcast - the same process without any state or memory beyond the immediate receipt (hence, called Amnesiac Flooding (AF)), due to some still slightly mysterious properties of simple undirected graphs, terminates in asymptotically optimal time on every graph. Intriguingly, we have recently discovered [DISC2025] that AF is Unique! i.e. under certain reasonable conditions, AF is the one and only algorithm that achieves terminating broadcast. Are there other examples of Unique algorithms in literature, and is counting the number of algorithms for solving a problem a concept we can reasonably postulate?

AF on Wikipedia: https://en.wikipedia.org/wiki/Amnesiac_flooding

Speaker Bio:
Amitabh Trehan is an associate professor at the department of Computer Science, Durham University, U.K., where he heads the NESTiD (Network Engineering, Science, and Theory in Durham) research group. In the academic year 2025-26, he’s on a sabbatical reconnecting with Indian academia! He is currently a visiting professor in the CSE Department at IIT Madras.

Speaker: All CSE Research Scholars

Date: Feb 28, 2026

Time: 09:30 AM

Venue: SSB 334 (A M Turing Hall) and CSB 13

Abstract:

Talks (9:30 AM - 12:15 PM) in AM Turning Hall (SSB 334) and Posters (2 PM - 7 PM) in CSB 13

Speaker: G Mahesh (CS22S009)

Date: Feb 26, 2026

Time: 03:00 PM

Venue: MR1 (SSB 233, First Floor)

Abstract:

Embedded firmware is a critical component of Internet-of-Things (IoT) devices deployed in security-critical domains. Automated vulnerability discovery for such firmware remains challenging due to its tight coupling with the underlying hardware and the absence of source code or detailed specifications. While emulation-based firmware fuzzing has shown promise, existing approaches rely on coarse or heuristic peripheral models that fail to handle complex validation logic, limiting exploration of deep execution paths.
We present FlashFuzz, a fuzzing framework that enables effective exploration of embedded firmware by accurately modeling peripheral dependent control flow. FlashFuzz identifies peripheral input entry points and tracks the propagation of peripheral data through firmware transformations using lightweight taint analysis. By correlating peripheral reads with conditional branches, FlashFuzz selectively extracts and solves constraints imposed by firmware checks to synthesize concrete inputs that steer execution past validation barriers. To maintain scalability, FlashFuzz limits expensive symbolic reasoning and leverages static analysis to infer input sizes and semantic properties.
We implement FlashFuzz on an emulation-based fuzzing platform and evaluate it on 22 real-world firmware binaries, demonstrating improved code coverage and enhanced vulnerability discovery compared to state-of-the-art firmware fuzzers.

Speaker: Chhaya (postdoc at the Indian Statistical Institute, Kolkata)

Date: Feb 26, 2026

Time: 02:00 PM

Venue: SSB 334 (A M Turing Hall)

Abstract:

In the graph stream model of computation, an algorithm processes the edges of an n-vertex input graph in one or more sequential passes while using a memory that is sublinear in the input size. The streaming model poses significant challenges for algorithmically constructing long paths. Many known algorithms that are tasked with extending an existing path as a sub-routine require an entire pass over the input to add a single additional edge. This raises a fundamental question: Are multiple passes inherently necessary to construct paths of non-trivial lengths, or can a single pass suffice? To address this question, we systematically study the Longest Path problem in the one-pass streaming model. In this problem, given a desired approximation factor α, the objective is to compute a path of length at least lp(G)/α, where lp(G) is the length of a longest path in the input graph G.

We give algorithms as well as space lower bound results for both undirected and directed graphs. Besides the insertion-only model, where the input stream solely consists of the edges of the input graph, we also study the insertion-deletion model, where previously inserted edges may be deleted again. Our results include:
1. We show that for undirected graphs, in both the insertion-only and the insertion- deletion streaming models, there are semi-streaming algorithms, i.e., algorithms that use space O(n poly log n), that compute a path of length at least d/3 with high probability, where d is the average degree of the input graph. These algorithms can also yield an α-approximation to Longest Path using space \tilde O(n^2/α).
2. Next, we show that such a result cannot be achieved for directed graphs, even in the insertion-only model. We show that computing a (n^{1−o(1)})-approximation to Longest Path in directed graphs in the insertion-only model requires space Ω(n^2). This result is in line with recent results that demonstrate that processing directed graphs is often significantly harder than undirected graphs in the streaming model.
3. We further complement our results with two additional lower bounds. First, we show that semi-streaming space is insufficient for small constant factor approximations to Longest Path for undirected graphs in the insertion-only model. Last, in undirected graphs in the insertion-deletion model, we show that computing an α-approximation requires space Ω(n^2/α^3).

Speaker Bio:
Chhaya has a PhD in mathematics from the London School of Economics & Political Science. Prior to doing a PhD she has worked in tech Industry for 8 years in various capacities. She is currently doing a postdoc at the Indian Statistical Institute, Kolkata.

Speaker: Nagashri Krishnakumar (IIT Madras)

Date: Feb 24, 2026

Time: 04:00 PM

Venue: SSB 334 (A M Turing Hall)

Abstract:

Solving Mazes - more formally, the graph reachability is a fundamental algorithmic problem in space complexity: given a graph and two special vertices $s$ and $t$, the task is to determine if there is a path from $s$ to $t$ in the graph. While the directed reachability is complete for $NL$, the undirected reachability is $L$-complete. The word problem is a fundamental computational problem over a groupoid $(mathcal{A, ullet})$: given a word over the alphabet $mathcal{A}$, the task is to determine if the word evaluates to an element in $mathcal{A}$ w.r.t. the operation $ ullet$. The word problem is undecidable even for finitely presented groups.

A bridge between the Reachability and Word problem: the Labelled Reachability problem for undirected graphs where the edge labels are monoid elements is known to capture space-bounded complexity classes $L$ and $NL$. Given a labelled graph $G(V, E)$ (labelled with $phi: E o M$), $s,t in V$ and an accepting subset $F subseteq M$, the problem asks whether there is a walk $P$ from $s$ to $t$ in $G$ where $phi(P) in F$. When the accepting element is also a part of the input, the problem has been studied by Ramaswamy {em et al} (2019) for the case when the monoid is aperiodic and when it is a group.

Motivated by the success of space-bounded algorithms for the graph reachability in the undirected case, we study the labelled reachability when the accepting set is also fixed. We establish upper and lower bounds for undirected labelled reachability over various monoids and accepting subsets. We give a logspace algorithm for reachability over all monoids when the accepting set is the monoid identity and show $NL$-hardness when the accepting element is a restricted idempotent. We also consider arbitrary accepting subsets over commutative monoids and restricted union of groups monoid to show logspace algorithms, and dichotomies for the building blocks of aperiodic monoids.

Speaker: Dr. Partha Ranganathan

Date: Feb 23, 2026

Time: 10:00 AM

Venue: DSAI, Room No. 606

Abstract:

Abstract: We are in the middle of an intelligence revolution, with impactful new AI innovations across various sectors from consumer products to enterprise cloud offerings, and even fundamental scientific research. These amazing advances have been made possible by equally impressive progress in computing infrastructure. But as we look at continued exponential growth, the growth, volatility, and diversity of the rapid pace of innovation demands dramatic improvements in compute efficiency, reliability, and sustainability. This talk will discuss disruptive innovations and new opportunities: from “mud to cloud,” from datacenter infrastructure to broader cloud computing services; and from “chip to ship,” from the design of hardware to their deployment and usage in production. Codesign and collaboration - across the hardware-software stack, across disciplines, and across communities - will be key to this exciting new future.

Bio: Partha Ranganathan is currently a VP, Technical Fellow at Google where he is driving next-generation computing systems for the AI-era. He has pioneered numerous impactful innovations touching billions of users, including widely-adopted ideas across all mobile and cloud systems. He has published 100+ papers, is the co-author of the popular Datacenter as a Computer textbook, and is a co-inventor on 125+ patents. He has been recognized with numerous awards; notably: top 35 young innovators in the world by MIT Tech Review, top-15 enterprise technology rock star by Business Insider, IEEE & ACM Fellow, and Rice University & IIT Madras distinguished alumni awards. Fun fact: Partha is one of the few computer scientists to also have an Emmy award!

To mark the occasion, we will be hosting lunch with the guest at BEGH, and we would be happy to have interested faculty members join us

Speaker: Robert Samuel (CS23S042)

Date: Feb 19, 2026

Time: 04:00 PM

Venue: MR1 (SSB 233)

Abstract:

This work presents DHIR (Distributed Heterogeneous IR), a task-based intermediate representation for compiling programs to modern HPC clusters with multi-core CPUs and accelerators such as GPUs. The core idea is to represent cluster execution explicitly in the compiler IR: programs are decomposed into tasks, tasks are mapped to target devices/nodes, and data movement and synchronization requirements are made visible so the compiler can generate correct distributed code. DHIR is implemented as an MLIR dDHIRialect so it can interoperate with existing MLIR infrastructure. It provides three core abstractions: (1) dhir.task, which encapsulates a unit of work together with explicit read/write memory sets and a device target; (2) dhir.partition, which marks dependence-free loop iteration spaces that can be safely distributed across devices and then lowered into multiple tasks; and (3) dhir.schedule, which acts as the top-level orchestration scope where the compiler builds a task dependency graph (RAW/WAR/WAW), assigns tasks to devices using target information, and inserts necessary communication and synchronization when dependencies cross device boundaries. Using this approach, a single source program can be retargeted across different cluster configurations (CPU-only, GPU-only, or heterogeneous CPU+GPU) by recompiling with a different device/topology configuration, instead of rewriting large amounts of MPI/OpenMP/CUDA code by hand. In our evaluation on representative PolyBench kernels, DHIR-generated code achieves performance close to hand-optimized implementations while substantially reducing developer effort for porting and retargeting.

Speaker: Ajay Singh, ICS FORTH, Greece

Date: Feb 11, 2026

Time: 02:30 PM

Venue: SSB 334 (A M Turing Hall)

Abstract:

Safe memory reclamation (SMR) is crucial to ensure memory safety in optimistic and lock-free concurrent data structures in non-garbage collected programming languages. Yet, designing an ideal SMR algorithm remains challenging. The main difficulties include achieving high speed and scalability, keeping the interface easy to use for programmers, ensuring applicability to a broad class of data structures, bounding the memory footprint, and avoiding asymmetric overhead across data structure operations. Addressing these issues is critical for enabling the deployment of concurrent data structures in production systems.


In this talk, I will present three new methods for safe memory reclamation that are each designed to address a distinct shortcoming of state-of-the-art safe memory reclamation algorithms. Together, these methods demonstrate how codesigning safe memory reclamation algorithms with neighboring layers of the programming environment, including operating system and hardware cache-coherence, can overcome longstanding challenges efficiently.

Speaker Bio:
Ajay Singh obtained his PhD in Computer Science from University of Waterloo in 2024. His Life's goal is to build data structures and algorithms for high performing next generation concurrent systems. He is a recipient of the Distinguished Paper Award at PPoPP 2025, the Best Artefact Award at PPoPP 2021, the David R Cheriton Graduate Scholarship (awarded to top graduate students of the department) 2022. Currently, he is a postdoctoral researcher at Institute of Computer Science (ICS) FORTH in Greece, working with Panagiota Fatourou. Before his PhD he worked as Software Engineer at Samsung Research Institute Noida where he contributed to development of successful feature phones such as Samsung Guru, Samsung Metro, Samsung Guru FM Plus.

Speaker: Dhara Thakkar, Nagoya University, Japan

Date: Feb 06, 2026

Time: 11:15 AM

Venue: SSB 334 (A M Turing Hall)

Abstract:

In this talk, I will discuss recent progress on the role of classical proofs in quantum complexity theory, focusing on group-theoretic problems in the black-box model. In particular, I will present QCMA protocols for two long-standing open questions in this area. First, we show that the Group Non-Membership problem--known to lie in QMA but not in MA--is in fact in QCMA, settling a 2006 conjecture by Aaronson and Kuperberg. This result follows from a more general result that the Group Order Verification problem lies in QCMA, answering an open question posed by Watrous in 2000. Our techniques also give improved quantum upper bounds on the complexity of many other group-theoretical problems, such as group isomorphism in black-box group settings.

This talk is based on the joint work with François Le Gall and Harumichi Nishimura.

Speaker Profile:
Dhara Thakkar is currently a Designated Assistant Professor at the Graduate School of Mathematics, Nagoya University. She completed her PhD in Theoretical Computer Science at IIT Gandhinagar. Her PhD thesis was awarded the ACM India Doctoral Dissertation Award 2025. Her research interests are in theoretical computer science, in particular, Algebraic Computation, Computational Complexity Theory, Group Theory, Quantum Complexity Theory, Group-based Cryptography, Algorithms and Data Structures, and Parallel Algorithms.

Speaker: Gayathri S (CS23S043)

Date: Feb 06, 2026

Time: 10:00 AM

Venue: SSB 334 (A M Turing Hall)

Abstract:

Speculative execution is a cornerstone of performance optimization in modern out-of-order processors, yet it has introduced a broad class of microarchitectural side channels. This talk investigates performance-induced security vulnerabilities that arise from aggressive memory disambiguation mechanisms in speculative processors. While most prior defenses focus on speculative data leakage, recent work has shown that the memory ordering logic itself can leak fine-grained structural information through deterministic timing variations, enabling unprivileged adversaries to infer address mappings and amplify other microarchitectural attacks. A central challenge is that these vulnerabilities stem directly from performance-critical speculation mechanisms, creating an inherent challenge in balancing security and efficiency. Traditional mitigation approaches either disable speculation entirely or introduce prohibitive performance overheads, making them impractical for deployment. This thesis presents a lightweight hardware defense that mitigates these attacks by obfuscating deterministic patterns in speculative memory-dependency resolution while preserving the performance benefits of aggressive out-of-order execution. We validate the proposed approach through cycle-accurate microarchitectural simulation and hardware synthesis, demonstrating effective suppression of timing-based leakage with negligible performance degradation and minimal hardware cost. This work contributes both a practical defense mechanism and insights into design principles for reconciling performance-oriented speculation with security requirements in future processor architectures.

Speaker: Anil Kumar (CS18D001) Thesis defense

Date: Jan 29, 2026

Time: 11:00 AM

Venue: Online

Abstract:

The Santa Claus Problem, also known as the Max-Min Fair Allocation Problem, is a fundamental NP-hard allocation problem in which a set of gifts must be distributed among a set of kids. Each gift provides a kid-dependent happiness value, and the total happiness of a kid is the sum of the happiness values of the gifts assigned to them. The objective is to allocate gifts so as to maximize the minimum total happiness received by any kid. A widely studied variant is the Restricted Santa Claus Problem, where each gift gives a uniform non-zero happiness value to a subset of kids and zero to the rest.

In this work, we study the problem from the perspective of approximation algorithms using nonlinear mathematical programming techniques. We design polynomial time approximation algorithms for the Restricted Santa Claus Problem by combining the kid–gift clustering technique of Bansal and Sviridenko, which we refer to as BS-Clustering, with geometric programming. This approach yields a (12 + ϵ) approximation algorithm, improving upon the previous 36-approximation bound. We further introduce the (τ, α, ϵ)-Santa Claus Problem, in which the input is a quadruple (I, τ, α, ϵ), where I is a Santa Claus instance, τ, α ≥ 1, and ϵ ∈ (0, 1). It is guaranteed that the instance admits an allocation in which each kid has happiness at least τ / α. Using geometric programming, we design a polynomial time algorithm that computes an allocation guaranteeing happiness at least τ / (α+ϵ) for every kid. As a consequence, we obtain a polynomial time (3.534 + ϵ) approximation algorithm for the Restricted Santa Claus Problem, improving upon the previously best known (4 + ϵ) bound.


We also investigate the parameterized complexity of the Restricted Santa Claus Problem with respect to structural parameters of the incidence graph, including treewidth (ω), clique-width (λ), diameter (δ), and the target happiness value (τ ). We show that the problem is W[1]-hard under the combined parameters (ω, λ, δ), even when the incidence graph is planar, and under (τ, λ, δ). On the positive side, we establish fixed-parameter tractability of the general Santa Claus Problem
under the combined parameters (ω, τ ) and (m, τ ), where m is the number of kids.

Speaker: Nikhil Shinde (CS23S018)

Date: Jan 29, 2026

Time: 10:00 AM

Venue: SSB 334 (A M Turing Hall)

Abstract:

Programmable data-plane (PDP) switches enable flexible packet processing
but remain constrained in scheduling capabilities, particularly for
priority-based policies that require strict ordering of packets
according to user-defined ranks. Push-In First-Out (PIFO) provides an
ideal abstraction for programmable packet scheduling; however, its
requirement for line-rate packet sorting makes it impractical at high
network speeds (100G and beyond). PIFO is a priority queue that enables
ordering enqueued packets based on their priority. Alternate accurate
schedulers like SIFTER, involve complex packet movement between the
scheduling queues. Approximate schedulers such as SP-PIFO and AIFO, RIFO
reduce complexity but introduce priority inversions, degrading latency,
fairness, and flow completion times (FCTs) as they rely on First-In
First-Out (FIFO) queues or use Active Queue Management (AQM) as a
substitute to scheduling. To address the scalability limitations of
accurate schedulers while avoiding the correctness issues of approximate
schedulers, this work proposes two architectures -- called P3PO and
PPIFO -- that are scalable, inversion-free and parallelize the sorting
workload across multiple priority queues.

P3PO and PPIFO decompose a large global priority queue into multiple
smaller, bounded-capacity priority queues that operate in a parallel
manner. P3PO uses a cascaded set of priority queues with priority-based
bounds to ensure that packets are inserted into the earliest queue
capable of maintaining ordering; overflow is handled by cascading
evictions into lower-priority queues. Under-utilization of a queue
triggers promotion of packets from lower priority queues to higher
priority queues to maintain availability for timely dequeue. PPIFO
distributes packets across multiple independent priority queues based on
occupancy, using a de-multiplexer for balanced enqueue and a multiplexer
for globally selecting the highest-priority packet at dequeue. Both
designs ensure bounded sorting complexity, preserve strict priority
ordering, and eliminate priority inversions.

The architectures are implemented in the NetBench packet-level
simulator, and evaluated using empirical datacenter workloads
(Web-search and Data Mining) under in-cast and all-to-all traffic
patterns. Experiments are conducted on star and leaf-spine topologies
using Start-Time Fair Queueing (STFQ) and pFabric-style ranking. Results
show that P3PO achieves fairness and flow completion time (FCT)
performance comparable to ideal PIFO and performs better than
approximate schedulers. We show that P3PO and PPIFO have less packet
comparisons as compared to ideal PIFO, thus reducing the sorting
latency. For flows under 2 MB, P3PO improves FCTs by 14–62%, and for
flows exceeding 2 MB by 47–60% as compared to approximate
schedulers. Packet drops are reduced by 66–95% due to improved queue
utilization and elimination of inversion-driven tail latencies against
approximate schedulers.

Speaker: Ritwik Badola (CS22M016)

Date: Jan 28, 2026

Time: 11:00 AM

Venue: MR1 (SSB 233, First Floor)

Abstract:

This talk investigates the security posture of small office/home office (SOHO) internet-connected Wi-Fi routers and IP-camera devices through an end-to-end supply chain lens by analysing device firmware. Using a multi-vendor corpus and automated scanning, we quantify vulnerability and patch lag, map operating system kernel baselines to publicly known kernel issues and fixes, and use limited lifecycles and market signals to contextualise whether affected devices remain present in the ecosystem. Across vendors, including brand-new devices procured off the shelf in 2025, we find that many devices run significantly outdated operating system kernels with large backlogs of publicly disclosed vulnerabilities (CVEs) present in them, and often bundle additional third-party components (TPCs) that are similarly old and vulnerability-prone.


A central finding is that these devices vendors are effectively locked to specific kernel versions by system-on-chip (SoC) SDKs; Wi-Fi router and IP-camera makers often remain on older kernels to retain chipset support and SoC vendor-provided proprietary software components. This produces a vulnerability debt that is inherited along the supply chain from SoC vendors to device manufacturers to device vendors and ultimately borne by end users. We further show that kernel upgrades are possible and plausible on supported platforms by contrasting with OpenWRT-based maintenance models, highlighting how open-source driver enablement can reduce upgrade cost and friction. We present a platform and SDK-aware analysis framework, report empirical findings across vendors, and discuss lifecycle and policy gaps, along with limitations and areas requiring further validation, and what these results imply for improving updates and reducing long-lived risk at in these devices at the network edge.

Speaker: Ashesh Ashesh (Milan Italy)

Date: Jan 22, 2026

Time: 02:30 PM

Venue: SSB 233 (ALC MR1)

Abstract:

Fluorescence microscopy is limited by optics, fluorophore chemistry, and photon exposure,
forcing trade-offs in speed, resolution, and depth. In this talk, I will discuss my PhD research
that addresses these challenges. Specifically, my PhD research enables imaging of multiple cellular structures within a single fluorescent channel, allowing faster imaging with less photon exposure. Technically speaking, given a superimposed image (e.g., containing nucleus and tubulin), the objective is to predict the constituent images separately.

This talk focuses on my first work, μSplit [1]. Early in my PhD, we found that regular deep architectures performed best with large image patches, but GPU memory limits hindered scalability. We thus developed μSplit, a novel meta-architecture enabling memory-efficient use of large image context. Built on Hierarchical-VAE (HVAE) and U-Net variants, it modifies HVAE’s ELBO loss for non-autoencoding tasks, modifies KL loss for high-frequency details extraction, and reformulates the encoder output for stable training. We also created a synthetic dataset to evaluate our network’s capability to extract large image context. Lastly, we explored tiling artifacts, analyzed two mitigation strategies, and demonstrated the superiority of one, both empirically and via out-of-distribution arguments.

References: [1] Ashesh Ashesh, Alexander Krull, Moises Di Sante, Francesco Pasqualini, and Florian Jug. μSplit: Image decomposition for fluorescence microscopy. ICCV, 2023.


Speaker Bio:
Ashesh is a postdoctoral fellow at Human Technopole, Milan, Italy. He recently completed his PhD in Computer Science at TU Dresden, Germany, conducted in Florian Jug’s lab at Human Technopole’s Computational Biology Center.
His doctoral research focused on image decomposition, specifically unmixing superimposed fluorescence microscopy images into constituent channels. With first-author publications in top CV/ML venues such as ECCV, ICCV, and NeurIPS, and a recent one accepted to Nature Methods, his work offers a robust solution to this challenge. His thesis earned a nomination for TU Dresden’s PhD prize nominations (pending decision), an €8,700 EMBO grant for a research visit to ENS de Lyon on self-supervised finetuning and uncertainty quantification, and the Best Oral Presentation Award at the 2024 HT PhD & Postdoc Symposium.
Previously, Ashesh earned a dual B.Tech+M.Tech in Computer Science (2015) from IIT Delhi,
India. He brings over three years of industry experience as a Data Scientist and served as Research Assistant at National Taiwan University under Prof. Hsuan-Tien Lin, initiating multiple computer vision projects, culminating in publications.

Speaker: Chaitanya Agarwal (New York University)

Date: Jan 19, 2026

Time: 02:00 PM

Venue: SSB 134

Abstract:

Authenticated data structures (ADSs) allow untrusted third parties to carry out operations which produce proofs that can be used to verify an operation’s output. Such data structures are challenging to develop and implement correctly. In this talk, I will talk about programming frameworks that exploit some structural properties of ADSs to make the task of correctly implementing ADSs easier: (1) lambda-auth - a domain-specific extension of the OCaml programming language, that generates correct and secure ADS binaries automatically; (2) Authentikit - a library version of lambda-auth currently implemented in OCaml. I will also talk about recent work by us (https://dl.acm.org/doi/abs/10.1145/3719027.3744801) that gives a formal proof of security and correctness of Authentikit.

Speaker Bio: Chaitanya Agarwal (https://culechetoo.github.io) is a 3rd year computer science PhD student at the New York University, advised by Joseph Tassarotti. He is broadly interested in programming languages and formal verification with a particular focus on verification of security applications. In the past, he has also worked with Thomas Wies on abstract-interpretation analysis for recursive, higher-order programs, and with Shibashis Guha, on developing statistical-model-checking techniques for Markov Decision Processes (MDPs). Chaitanya obtained his B.Tech. from IIIT Delhi.

Speaker: Naresh Goud Boddu (VP, JP Morgan Singapore)

Date: Jan 14, 2026

Time: 10:00 AM

Venue: SSB 334 (A M Turing Hall)

Abstract:

Tamper-detection codes (TDCs) are fundamental objects at the intersection of cryptography and coding theory. A TDC encodes messages in such a manner that tampering with the codeword causes the decoder to either output the original message or reject it. In this work, we study quantum analogs of one of the most well-studied adversarial tampering models: the so-called t-split-state tampering model, where the codeword is divided into t shares and each share is tampered with locally. It is impossible to achieve tamper detection in the split-state model using classical codewords. Nevertheless, we demonstrate that the situation changes significantly if the message can be encoded into a multipartite quantum state entangled across the t shares. Concretely, we define a family of quantum TDCs on any t ≥ 3 shares, which can detect arbitrary split-state tampering so long as the adversaries are unentangled, or even limited to a finite amount of pre-shared entanglement. Previously, this was only known in the limit of asymptotically large t. As our flagship application, we show how to augment threshold secret sharing schemes with similar tamper-detecting guarantees. We complement our results by establishing connections between quantum TDCs and quantum encryption schemes.

Speaker Bio:
Naresh Goud Boddu is Vice President and Applied Research Lead at J.P. Morgan Singapore. He completed his Ph.D. (Thesis) in September 2022 under Prof. Rahul Jain at the Centre for Quantum Technologies, National University of Singapore. Following his Ph.D., he was a Postdoctoral Researcher at NTT Research, where he worked with Prof. Vipul Goyal and Prof. Dakshita Khurana until November 2024. At J.P. Morgan, he has worked on lattice-based zero-knowledge proof applications for financial institutions. His research interests lie at the intersection of post-quantum cryptography, quantum cryptography, and quantum information. More information is available at https://sites.google.com/view/ngboddu/home

Speaker: Pratap Singh (Carnegie Mellon University)

Date: Jan 13, 2026

Time: 11:00 AM

Venue: SSB 334 (A M Turing Hall)

Abstract:

Cryptographic security protocols, such as TLS or WireGuard, form the foundation of a secure Internet, but vulnerabilities are discovered in them with alarming frequency. Formal verification promises a foundational solution to this problem, with significant prior work on mechanizing cryptographic proofs of high-level protocol designs, and more recent work on verifying particular implementations of single protocols against higher-level specifications.

In this talk, I will discuss our work on Owl, a verifier and secure compiler for cryptographic protocols. Owl's verifier uses a novel combination of information-flow and refinement types to prove security in the computational model, enabling greater modularity and automation than prior computational tools. Owl's compiler translates well-typed protocols into performant, interoperable, side-channel-resistant Rust libraries that are automatically verified to be correct. With Owl, developers can define and prove security for their protocols in an intuitive, high-level language, and obtain for free a drop-in executable implementation with formal guarantees of correctness and security.

We evaluate Owl using a range of case studies. We verify the core logic of 14 protocols, including SSH and Kerberos. We additionally develop two large-scale, interoperable case studies for WireGuard and Hybrid Public-Key Encryption (HPKE), yielding verified implementations that interoperate with, and match the performance of, existing industrial baselines on end-to-end benchmarks.

Speaker Bio:
Pratap Singh is a fourth-year PhD student in Computer Science at Carnegie Mellon University, advised by Bryan Parno. His research leverages formal methods techniques to produce provably secure systems, exemplified by the Owl tool for verified cryptographic protocol implementations. He received a bachelor's degree from Harvard University in 2021, where he worked with Stephen Chong on compiler correctness proofs and Adam Chlipala on the Bedrock2 verified compiler. He is supported by the NSF Graduate Research Fellowship, and his research has received the Distinguished Artifact Award at USENIX Security.

Speaker: Ms. Srividhya S (CS23S024)

Date: Jan 13, 2026

Time: 11:00 AM

Venue: MR1 (SSB 233, First Floor)

Abstract:

Dynamic pricing in high-dimensional markets poses fundamental challenges of scalability, uncertainty, and interpretability. Existing low-rank bandit formulations learn efficiently but rely on latent features that obscure how individual product attributes influence price. We address this by introducing an interpretable Additive Feature Decomposition-based Low-Dimensional Demand (AFDLD) model, where product prices are expressed as the sum of attribute-level contributions and substitution effects are explicitly modeled. Building on this structure, we propose ADEPT (Additive DEcomposition for Pricing with cross elasticity and Time-adaptive learning) - a projection-free, gradient-free online learning algorithm that operates directly in attribute space and achieves a sublinear regret of O (√\uD835\uDC51\uD835\uDC47^{3/4}). Through controlled synthetic studies and real-world datasets, we show that ADEPT (i) learns near-optimal prices under dynamic market conditions, (ii) adapts rapidly to shocks and drifts, and (iii) yields transparent, attribute-level price explanations. The results demonstrate that interpretability and efficiency in autonomous pricing agents can be achieved jointly through structured, attribute-driven representations.

Speaker: Prof. Venkatesan Guruswami (University of California, Berkeley)

Date: Jan 07, 2026

Time: 11:00 AM

Venue: SSB 334 (A M Turing Hall)

Abstract:

We show that any binary linear code of block length  n that is locally correctable with 3 queries against a constant fraction of adversarial errors must have dimension at most $O(\log^2 n \log \log n)$. This nearly matches the known construction of 3-query locally correctable codes (LCCs) based on quadratic Reed–Muller codes, which have dimension $\Theta(\log^2 n)$. Our result significantly improves the best known upper bounds in the binary case: the $O(\log^8 n)$ bound of Kothari and Manohar (STOC 2024), later improved to $O(\log^4 n)$ by Yankovitz (FOCS 2024).
Prior work bounded the dimension of 3-query LCCs by reducing them to 2-query locally decodable codes and invoking strong known bounds for the latter. Our approach is more direct and proceeds by bounding the covering radius of the dual code, borrowing inspiration from (Iceland and Samorodnitsky, 2018). Specifically, we show that in any 3-query LCC with encoding map $x \mapsto (v_1 \cdot x, \dots, v_n \cdot x)$, every binary vector of length k can be expressed as a $\tilde{O}(\log n)$-sparse linear combination of the $v_i$'s. This then yields the desired dimension bound via a simple counting argument.

The crux of our proof is a procedure that compresses any sufficiently large linear combination of the $v_i$’s into a sparser one, by exploiting the abundance of short linear dependencies amongst them. This step hinges on a recent result of Alon, Bucić, Sauermann, Zakharov, and Zamir (2023) on the existence of rainbow cycles in properly edge-colored graphs. We apply this theorem in a black-box manner to graphs that capture the combinatorial structure induced by the local correction constraints.

Joint work with Omar Alrabiah.

Speaker Bio:
Prof. Venkatesan Guruswami is the Chancellor's Professor at the Dept of EECS, Professor at the Dept of Mathematics, and the Director of the Simons Institute for the Theory of Computing at UC Berkeley. Dr Guruswami's research interests span several topics in theoretical computer science, including the theory of error-correcting codes, the approximability of fundamental optimisation problems, explicit combinatorial constructions, pseudorandomness, probabilistically checkable proofs, computational complexity theory, and algebraic algorithms.

Dr. Guruswami currently serves as the Editor-in-Chief for the Journal of ACM and has in the past served as the Editor-in-Chief for the ACM Transactions on Computation Theory. Dr. Guruswami is a recipient of the Presburger Award (2012), Packard Fellowship (2005), Sloan Fellowship (2005), NSF CAREER award (2004), the ACM Doctoral Dissertation Award (2002), and the IEEE Information Theory Society Paper Award (2000).

Speaker: Prof. Jeffrey Ullman (Stanford University)

Date: Jan 05, 2026

Time: 02:30 PM

Venue: SSB 334 (A M Turing Hall)

Abstract:

We shall introduce four algorithms that run very fast on large amounts of data, although typically the answers they give are approximate rather than precise. (1) Locality-sensitive hashing (2) Approximate counting (3) Sampling (4) Counting triangles in graphs.

Speaker: Sharat Ibrahimpur (Faculty Candidate)

Date: Jan 05, 2026

Time: 11:30 AM

Venue: SSB 334 (A M Turing Hall)

Abstract:

Uncertainty is ubiquitous in real-world problems, highlighting a growing need for new mathematical and algorithmic tools for optimization under uncertainty. In this talk, I will discuss two prominent hurdles that arise in stochastic combinatorial optimization, along with recent advances that address these challenges.


The first setting considers a generic combinatorial optimization problem in which the costs are random variables with known distributions, and feasible solutions induce multi-dimensional cost vectors. The algorithmic goal is to compute an oblivious solution that minimizes the expected norm of the associated cost vector for a given monotone, symmetric norm. One can show that optimizing the norm of the expected cost vector may yield solutions whose approximation quality degrades with the dimensionality of the problem. I will present a powerful theorem, dubbed approximate stochastic majorization, that enables constant-factor approximations for norm-based objectives across a wide class of combinatorial optimization problems.


I will then turn to stochastic decision environments where forgoing adaptivity for simplicity or analytical convenience can lead to poor approximation guarantees. I will illustrate this through a novel variant of two-stage stochastic load balancing that enables a quantitative trade-off between the practical benefits of non-adaptive algorithms and their performance limitations. I will present a striking power-of-two-choices result for stochastic load balancing, showing that constant-factor approximations are achievable with limited adaptivity relative to the omniscient and adaptive optimums.

Speaker Bio:
Sharat Ibrahimpur (https://i-sharat.github.io/) is a postdoctoral researcher in the Computer Science department at ETH Zurich. Previously, he held postdoctoral positions at the University of Bonn and the London School of Economics. Sharat earned his M.Math. and Ph.D. degrees in Combinatorics and Optimization from the University of Waterloo. He completed his undergraduate degree in Applied Mathematics at the Indian Institute of Technology Roorkee. Sharat's research focuses on designing approximation algorithms for combinatorial optimization problems, with an emphasis on optimization under uncertainty.

Speaker: Vaidy Sivaraman (Ohio University)

Date: Dec 26, 2025

Time: 10:00 AM

Venue: SSB 334 (A M Turing Hall)

Abstract:

Several topics connecting graph structure and graph invariants, particularly chromatic number, will be discussed. Several open problems and special cases of famous conjectures like Erdos-Hajnal conjecture will feature in this talk.

Speaker Bio:
Vaidy Sivaraman received his PhD in 2012 from The Ohio State University with Prof. Neil Robertson as his supervisor. He is currently an associate professor of mathematics at Mississippi State University. His research interests are in structural graph theory, mainly induced subgraphs, graph coloring, and hereditary graph classes. He is a recipient of the Simons Collaboration grant for mathematicians in 2021, and has been the dissertation supervisor of two PhD students. He has posed several problems and conjectures, some of which have been solved/resolved.

Speaker: Sugyani Mahapatra (CS18D015)

Date: Dec 22, 2025

Time: 11:00 AM

Venue: SSB 426

Abstract:

A graph representation of a complex system such as a biological or social system is often not a single "true" network, but a family of distinct yet related networks that together represent our knowledge of the system's interactions. For instance, multiple gene-gene networks could be learnt using observations of the same cell line from different time points, conditions, or bootstrap resamplings. Network science measures of nodes in such an ensemble of graphs could yield important insights about the underlying system's behaviors and dynamics.

Given this setting of multiple input graphs, each defined over the same set of nodes but having distinct yet similar/overlapping sets of edges, we can ask the following broad questions:
(1) Can we design algorithms to compute a network science measure (like node centrality) on this ensemble of graphs more efficiently than the naive approach of analyzing each input graph separately?
Such algorithms are feasible if the input graphs are similar to each other so that they can be organized hierarchically into a directed tree (arborescence), and the measure can be computed using dynamic/incremental algorithms. We have designed and earlier presented parameterized/approximation algorithms for the related problem of finding Steiner arborescence in a hypercube.
(2) Can we identify concrete applications (e.g., in biology) wherein ensemble analysis of multiple graphs leads to demonstrably robust insights?
Identifying hub genes in a gene-gene coexpression network is one such application, wherein we show that ensemble-based centrality analysis of genes can lead to gene rankings that are robust to uncertainty. In this talk, I will expand on this application by proposing an uncertainty-aware ranking of genes derived from an ensemble of centrality estimates, and comparing this ranking's performance to traditional centrality based rankings. In several simulated and real-world gene networks, across different evaluation measures pertaining to recovery of hub genes and tissue-specific pathways, our proposed gene rankings show noticeable performance gains over baseline rankings that do not incorporate uncertainty. Our ensemble analysis is more compute intensive though, and we are currently exploring if the hierarchical framework of organizing graphs described in (1) above can be used to improve running times in practice.

Overall, we present a concrete methodology that enables analysis of a collection of similar graphs inferred from measurements of a biological system to derive a stable prioritization of genes. As such, this work paves the way for similar integrative analyses of other system-level datasets in the future.

Speaker: Vignesh Manoharan (UT Austin, USA)

Date: Dec 19, 2025

Time: 03:00 PM

Venue: SSB 334 (A M Turing Hall)

Abstract:

Routing messages is an important problem in distributed networks, and efficient fault-tolerant routing requires methods to maintain shortest distances between nodes when faults occur. In this talk, I will introduce fault-tolerant versions of shortest path problems in graphs, and discuss algorithms and lower bounds for these problems in the "CONGEST" model of bandwidth-limited distributed computation. Specifically, I will present results for the Replacement Paths problem and the Distance Sensitivity Oracle problem, both of which deal with computing shortest paths in a graph when a single edge fails.

Speaker Bio: Vignesh Manoharan did his B.Tech (DD) in 2019 from IIT Madras. He finished his PhD from the University of Texas at Austin. His research interests include graph algorithms and fault tolerance, especially in parallel and distributed models of computation.

Speaker: Jayant Haritsa (IISc, Bengaluru)

Date: Dec 18, 2025

Time: 03:00 PM

Venue: SSB 334 (A M Turing Hall)

Abstract:

When complex SQL queries suffer slow executions despite query optimization, DBAs typically invoke automated query rewriting tools to recommend ``lean'' equivalents that are conducive to faster execution. The rewritings are usually achieved via transformation rules, but these rules are limited in scope and difficult to update in production systems. We investigate here how the remarkable cognitive capabilities of LLMs can be leveraged for performant query rewriting while incorporating safeguards and optimizations to ensure correctness and efficiency. Our study shows that these goals can be progressively achieved through incorporation of (a) an ensemble suite of basic prompts, (b) database-sensitive prompts via redundancy removal and selectivity-based rewriting rules, and (c) LLM token probability-guided rewrite paths. Further, a suite of logic-based and statistical tools can be used to check for semantic violations in the rewrites prior to DBA consideration. We have implemented the above LLM-infused techniques in the LITHE system, and evaluated complex analytic queries from standard benchmarks on contemporary database platforms. The results show significant performance improvements for slow queries, over both SOTA rewriters and the native optimizer. Overall, LITHE is a promising step toward viable LLM-based advisory tools for enhancing enterprise query performance.

Speaker: Shivika Narang

Date: Dec 17, 2025

Time: 11:00 AM

Venue: SSB 334 (A M Turing Hall)

Abstract:

We initiate the study of fair distribution of delivery tasks among a set of agents wherein delivery jobs are placed along the vertices of a graph. Our goal is to fairly distribute delivery costs (modeled as a submodular function) among a fixed set of agents while satisfying some desirable notions of economic efficiency. We adopt well-established fairness concepts -- such as envy-freeness up to one item (EF1) and minimax share (MMS) -- to our setting and show that fairness is often incompatible with the efficiency notion of social optimality. We then characterize instances that admit fair and socially optimal solutions by exploiting graph structures. We further show that achieving fairness along with Pareto optimality is computationally intractable. We complement this by designing an XP algorithm (parameterized by the number of agents) for finding MMS and Pareto optimal solutions on every tree instance, and show that the same algorithm can be modified to find efficient solutions along with EF1, when such solutions exist. The latter crucially relies on an intriguing result that in our setting EF1 and Pareto optimality jointly imply MMS. We conclude by theoretically and experimentally analyzing the price of fairness.

Joint work with Hadi Hosseini and Tomasz Was.

Speaker Bio: Shivika Narang is a postdoc at UNSW working with Haris Aziz and Toby Walsh, since March 2024. During Fall 2023, she was a postdoc at MSRI/SLMath in the Algorithms, Fairness and Equity program. She completed her PhD at the Indian Institute of Science, Bengaluru, advised by Prof Y Narahari. There, she was a recipient of the Tata Consultancy Services (TCS) Research Scholarship. Her current work is focused on fairness and efficiency in computational social choice, especially matching and allocation problems.

Speaker: Santhosh Raghul

Date: Dec 12, 2025

Time: 03:30 PM

Venue: SSB 334 (A M Turing Hall)

Abstract:

This presentation comprises two parts; these correspond to the courses CS6999 and CS7999, respectively. In the first part, we shall discuss a couple of celebrated results per-taining to cubic (that is, 3-regular) graphs from the literature, whereas the second part shall focus on our contributions to further the understanding of cubic graphs

Speaker: Dr. Kashyap Rajeevsarathy (IISER Bhopal)

Date: Dec 11, 2025

Time: 03:30 PM

Venue: CS 36 (CSB)

Abstract:

There are several infinite graphs associated with surfaces that combinatorially encode the simple closed curves on them. These graphs play a central role in the study of symmetries, topology, and the geometry of surfaces. In this talk, we will introduce one such graph, namely the curve graph, and some of its derivative graphs. We will discuss some basic properties of these graphs and their importance in the field of geometric topology.

Speaker Bio:
Dr. Kashyap Rajeevsarathy is a Professor and the Head of the Department of Mathematics at the Indian Institute of Science Education and Research (IISER) in Bhopal. He specializes in geometric topology, focusing on the mapping class groups of surfaces, while also having a secondary interest in algebraic graph theory. He earned his Bachelor's degree in mathematics from Vivekananda College in Chennai before pursuing his Master's degree at IIT Madras. He completed his Ph.D. in Mathematics at the University of Oklahoma in 2011, under the supervision of Professor Darryl McCullough. After completing his doctorate, he joined IISER Bhopal. He was awarded the Ramanujan National Fellowship from the Department of Science and Technology in 2011.

Speaker: Daniel Paul-Pena (University of California, Santa Cruz)

Date: Dec 09, 2025

Time: 03:00 PM

Venue: SSB 233 (MR1)

Abstract:

Subgraph and homomorphism counting are fundamental algorithmic problems. Recent work (Bera et al. SODA 2021, JACM 2022) provided a characterization of the patterns that can be counted in linear time for bounded degeneracy inputs. An older result by Nesetril and Ossona de Mendez proved that for input graphs in classes with bounded expansion all the patterns can be counted in linear time. What lies between? We present a hierarchy of dichotomies that closes the gap between both results, completely and precisely characterizing the instances that are linear time computable. The result uses ideas from graph sparsity, generalized notions of tree decompositions, and techniques from subgraph counting in sparse graphs. This is a joint work with C. Seshadhri.

Speaker Bio: Daniel Paul-Pena is a 5th year PhD Candidate at the University of California, Santa Cruz, under the supervision of Prof. C. Seshadhri. His main research interest is in subgraph counting, with special emphasis in finding algorithms that translate well into practice.

Speaker: Mr. S R Swamy Saranam Chongala (PhD Research Scholar, CS14D403

Date: Dec 08, 2025

Time: 11:00 AM

Venue: MR1

Abstract:

Modern applications depend on architectures that effectively exploit data locality, but growing working-set sizes have outpaced the scalability of SRAM-based caches. As a result, DRAM-based last-level caches are increasingly used, despite challenges such as large tag storage, higher access latency, and greater power consumption. This thesis addresses these limitations by proposing three techniques that leverage temporal, spatial, and algorithmic locality across the memory hierarchy and heterogeneous SoCs. First, we propose tagless DRAM cache (TDC) to mitigate the overhead of the tag array in DRAM caches and reduce average access latency. Our technique exploits the spatial locality exhibited by applications to design efficient large LLCs with minimal metadata overhead, while improving access latency and power consumption. In the second technique, we propose novel cache management strategies that decouple L3-L4 replacement decisions to reduce inter-cache interference. We introduce energy-efficient mechanisms tailored for tagless last-level caches (LLCs): restricted block caching (RBC) and victim tag buffer caching (VBC). These mechanisms incorporate L4 eviction penalties into L3 replacement logic with minimal overhead. Finally, building on the insights from locality exploitation in caches, we propose micro-architectural changes to efficiently harness algorithmic locality in SoCs with heterogeneous compute. Our technique aims to optimize data movement between CPUs and NPUs. We introduce a hybrid processing unit (HPU), a novel architecture that tightly integrates NPUs and CPUs. The HPU combines the strengths of both processors to improve data movement and performance for AI applications.

Speaker: Dr Tabish A. Syed (McGill University)

Date: Dec 08, 2025

Time: 10:00 AM

Venue: SSB 233

Abstract:

The rhythmic pumping of the mammalian heart arises from the intricately coordinated contraction of cardiomyocytes. However, the detailed three-dimensional organization of these cells has long been difficult to resolve. In this talk, I will introduce an integrated framework that applies computer vision methods to 3D confocal microscopy data to reconstruct cardiomyocyte orientation and geometry at micrometer resolution; an improvement of roughly three orders of magnitude over conventional approaches. I will show how this pipeline maps individual cardiomyocytes into coherent myofibers and further into higher-order laminar sheet structures that define ventricular architecture. By estimating orientation fields directly from volumetric microscopy data, we produce a comprehensive, multiscale reconstruction of myocardial organization at the cellular scale. Our work offers new insights into the structural basis of cardiac mechanics and establishes a foundation for high-resolution, data-driven models of heart function.

Speaker Bio:
Tabish A. Syed, is a Postdoctoral Fellow at the Centre for Neuroscience at McGill University Health Center-Research Institute. He earned his PhD in Computer Science from McGill University, specializing in computer vision with a focus on biological image analysis. His research focuses on developing well grounded explainable computational methods for biological image analysis. In the past his work has been featured on the cover of the EMBO Journal. He is particularly interested in geometry and applied math approaches for image analysis. His current work focuses on leveraging computer vision and machine learning techniques for uncovering the role of astroglia in freely behaving in mice, specifically, he is interested in exploring the roles of astrocytes in learning and behaviour.

Speaker: Nitin Saurabh (IIT Hyderabad)

Date: Dec 04, 2025

Time: 02:30 PM

Venue: SSB 334 (A M Turing Hall)

Abstract:

A polynomial p(x) is said to approximate a Boolean function f:{0,1}^n -> {0,1} if mod(f(x)-p(x)) <= 1/3 for all x in {0,1}^n. The approximate degree of f, denoted adeg(f), is defined to be the minimal degree of an approximating polynomial for f. It was introduced roughly 30 years back in a seminal work of Nisan and Szegedy (Computational Complexity 1994). Since then it has become a powerful and versatile tool in theoretical computer science finding spectacular applications in circuit complexity, quantum query complexity, communication complexity, computational learning, and differential privacy, to name a few. In a beautiful and significant work, Sherstov (Theory of Computing 2013) showed that adeg(f o g) = O(adeg(f)adeg(g)), where f o g is obtained by substituting variables of f by independent copies of g. The approximate degree composition problem posits that this upper bound is tight. That is, adeg(f o g) = Omega(adeg(f) adeg(g)) for all f and g. I will present a recent work of mine (along with my collaborators) on this problem. Furthermore, I will also present an overview of my research work and future plans.

Speaker Bio: Nitin Saurabh joined IIT Hyderabad CS Dept as a faculty member in 2022. Prior to that, he spent a brief stint at IIIT Hyderabad. Prior to that, he was a postdoctoral fellow at Max Planck Institut für Informatik, Saarbrücken, Germany and Charles University, Prague, Czech. He completed his PhD at the Institute of Mathematical Sciences (IMSc) in 2016 and did a BSc (Honours) in Mathematics and Computer Science from CMI in 2010.

Speaker: Kanchan Kumar Tiwari (IIT Madras)

Date: Nov 28, 2025

Time: 10:00 AM

Venue: SSB 334

Abstract:

This work will present DATURA, a Deep Learning(DL) based Adaptive Traffic-aware Unified Resource Auto-scaling framework for virtual network functions (VNFs) based slicing in 5G/6G networks. DATURA integrates a deep reinforcement learning (DRL) based traffic generator with a predictive GRU-MLP scaling architecture, forming a closed-loop, traffic-adaptive, and latency-aware scaling system. The framework addresses two key practical challenges that persist in existing predictive scaling solutions: the lack of realistic, dynamically varying traffic environments for evaluation, and the limited adaptability under non-stationary workloads. At the core of DATURA lies a Gated Recurrent Unit combined with a Multi-layer Perceptron (GRU-MLP) scaling controller, which forecasts per-VNF and per-slice latencies from streaming telemetry. Temporal dependencies are captured through the GRU layer, while two multitask MLP heads estimate local (per-VNF) and global (slice-level) latency trends. Once deployed, DATURA operates fully online, executing inference-driven scaling decisions in real time. The underlying models are periodically retrained with updated telemetry, enabling the framework to adapt to long-term traffic evolution without service disruption. The predicted latencies are then translated by a regression layer into proactive scaling decisions and resource allocations that maintain SLA compliance while avoiding unnecessary over-provisioning. This design replaces manual threshold tuning and online optimisation with a lightweight inference process that introduces negligible decision latency. Finally, a reactive safeguard layer ensures stability and robustness under unforeseen workload deviations. The DRL traffic generator employs Proximal Policy Optimisation (PPO) agents trained to learn transition probability matrices (TPM) that capture realistic transitions between low, medium, high, and very-high-load regimes. This enables the generation of controllable and bursty traffic traces that emulate real-world network fluctuations and stress-test scaling algorithms under reproducible conditions. The generator supports flexible composition of traffic patterns, enabling controlled mixes of load conditions that reflect realistic multi-slice behaviour and expose elasticity limits under contention. The framework is implemented in a SimPy-based 5G Core Network model for supporting UE registration and PDU session establishment, capturing control-plane dynamics. Detailed experiments for diverse traffic intensities show that DATURA consistently outperforms several existing schemes, achieving up to 73% latency reduction, 55% throughput gain, and 47% higher provisioning efficiency. These results demonstrate that DATURA provides a unified, traffic-aware, and data-driven solution for predictive and scalable VNF management in softwarised 5G/6G infrastructures.

Speaker: Dr. Akshima (NYU Shanghai)

Date: Nov 20, 2025

Time: 11:00 AM

Venue: SSB 334

Abstract:

In the preprocessing Decisional Diffie-Hellman (DDH) problem, we are given a cyclic group G with a generator g and of prime order N. We want to prepare some advice of size S, such that we can efficiently distinguish (g^x,g^y,g^xy) from (g^x,g^y,g^z) in time T for uniformly and independently chosen x,y,z from Z_N. This is a central cryptographic problem whose computational hardness underpins many widely deployed schemes, such as the Diffie-Hellman Key exchange protocol. Corrigan-Gibbs and Kogan [CK18] and then Coretti et al. [CDG18] studied lower bounds for this problem for generic algorithms. However, both the works left a gap from the best known (generic) attack for the problem. In our STOC24 paper, we close this gap up to poly-log factors and consequently show that DDH is asymptotically as hard as Discrete Logarithm problem for preprocessing algorithms. The talk will include some preliminary definitions, detailed description of the models, results and a high level idea of the techniques from the joint work with Tyler Besselman, Siyao Guo, Zhiye Xie and Yuping Ye, available at https://eprint.iacr.org/2024/1171.pdf.

Speaker: Dr. Siddharth Mehrotra (University of Amsterdam and Delft University of Technology (TU Delft))

Date: Nov 13, 2025

Time: 02:30 PM

Venue: Online

Abstract:

Trust is a cornerstone of any society. Nowadays, many AI systems are being developed that have the potential to make a difference in people’s lives, from health apps to robot companions. However, to reach their potential, people need to have appropriate levels of trust in these AI systems, i.e., people should not over- or under-trust AI as it can lead to misuse and disuse. Therefore, AI systems need to understand how humans trust them and what to do to promote appropriate trust. To investigate this question, in this talk I will adopt three lenses namely: a formal, a social and an application lens to ensure a holistic exploration of appropriate human trust, drawing on formal theories, social considerations, and practical insights. At first, we will delve into the technical intricacies by understanding the logic of building appropriate trust. Second, we will study the ways in which humans interact with and rely on AI systems and finally, we will apply these findings to a real-world context of predictive policing in the Netherlands by taking a deep dive. At the end, I will very briefly introduce some of my recent works on insurance as an interaction mechanism for trust calibration, findings on what is lacking in FAccT & AIES community to understand AI trustworthiness and designing a LLM digital companion for young adult informal caregivers.

Speaker: Rini Sharon (Uniphore)

Date: Nov 10, 2025

Time: 11:00 AM

Venue: SSB 233

Abstract:

This talk explores machine learning methods that bridge human cognitive signals and machine understanding. It covers my work on decoding speech and EEG to recognize imagined speech through multi-phasal modeling, improving decoding speed and generalizability in brain–computer interfaces. The second half extends into building scalable, multilingual speech systems, including but not limited to adaptive ASR, multimodal abuse detection, semantic endpointing in real-world conversational settings.

Speaker: Siddharth Priya (University of Waterloo)

Date: Nov 04, 2025

Time: 03:00 PM

Venue: SSB 334

Abstract:

Ensuring the correctness of systems software is critical, but traditional testing offers no formal guarantees. Formal verification provides stronger assurance, and bounded model checking has proven to be a particularly powerful approach. Yet, despite its promise, widespread adoption in everyday software development remains limited. This talk explores why — focusing on two core challenges: bridging the gap between developer intent and the design of verification tools, and advancing automated reasoning to scale verification to industrial programs. The speaker will share strategies for improving usability and demonstrate how enhanced reasoning can make formal verification more practical, scalable, and developer-friendly.

Speaker: Jagdeep Singh (Mississippi State University)

Date: Oct 28, 2025

Time: 04:00 PM

Venue: Online

Abstract:

Complement reducible graphs, or cographs, form one of the most well-understood hereditary classes of graphs: they admit linear-time recognition, possess multiple elegant characterizations, and have a simple forbidden subgraph description (no induced path of length three). In this talk, I will describe two natural generalizations of cographs; 2-cographs and sesquicographs. I will then present results showing that apexing (adding a single vertex or edge) preserves the finiteness of forbidden induced subgraphs, along with explicit bounds on their size. Finally, I will extend this framework from graphs to binary matroids, introducing comatroids as the natural matroid analogue of cographs. Analogous extension results hold in this setting. This work includes joint work with James Oxley (Electron. J. Combin., SIAM J. Discrete Math.), Thomas Zaslavsky and Vaidy Sivaraman (Discrete Math.) LINK: meet.google.com/agg-kgrr-ycp

Speaker: Dr. Kankana Roy (Karolinska Institute, Sweden)

Date: Oct 27, 2025

Time: 03:15 PM

Venue: SSB23

Abstract:

In this presentation, we will explore the problem of driver’s cellphone usage detection in vehicles for driver inattentiveness assessment. Current datasets in the literature, which are widely used in this domain to build and test models to be deployed in the real world, often suffer from class distribution bias, frequently overrepresenting inattentive behavior in the dataset to aid the supervised models. This imbalance may limit the generalizability of such models in practical, real-world driving conditions, where mobile usage is a relatively rare event. To address this challenge, we propose a novel approach using unsupervised dictionary learning by treating the problem as anomaly detection rather than supervised classification. This work illustrates one approach, combining hand detection, feature engineering, dictionary learning, and real-world applicability through a novel idea that reduces reliance on biased labels. Our results demonstrate comparable detection accuracy to fully supervised methods reported in the literature while offering better robustness to dataset imbalance. Overall, our study offers a practical and computationally efficient alternative to conventional supervised pipelines for driver inattentiveness detection, emphasizing generalizability and real-world feasibility.

Speaker: Pappu Kumar (CS20D015-IITM)

Date: Oct 24, 2025

Time: 03:30 PM

Venue: SSB 334

Abstract:

Leader election (LE) is one of the most fundamental and well-studied problems in distributed computing, with applications ranging from classical to modern systems. The obvious lower bounds on time and message complexity for explicit leader election are $Omega$(1) and $Omega$(n) on complete networks, and $Omega$(n) and $Omega$(n) on ring networks, respectively, where n is the number of nodes in the network. A long line of research has aimed at achieving bounds that are tight with respect to these lower bounds. In search of theoretically interesting results, the algorithms proposed in the past tend to be complex, hard to implement, and often hide large constants under asymptotic notation (e.g., big O), making them impractical in most scenarios. In this paper, we propose significantly simpler and easier-to-implement randomized leader election algorithms for asynchronous complete networks and asynchronous ring networks. We prove correctness for all our proposed algorithms. To study their performances, we simulated our algorithms along with several key algorithms from the literature using the NS-3 simulator, and conducted systematic performance comparison on large networks of about a million nodes. Our algorithms achieve less time and messages in our experiments than established LE algorithms. web conference link https://meet.google.com/yee-azeo-ujf

Speaker: Divyarthi Mohan (Boston University)

Date: Oct 24, 2025

Time: 02:00 PM

Venue: MR1

Abstract:

Digital markets and platforms have shaped the algorithmic landscape into a complex ecosystem of strategic, self-interested entities. This has motivated the study and development of mechanisms or algorithms that are robust to strategic behaviour, using tools from algorithms, game theory and economics. Standard assumptions in mechanism design are too strong to capture the informational challenges present in many real scenarios, from ad auctions where bidders' values depend on competitors' private market data, to resource allocation where there is uncertainty about future demands. In this talk, I will provide an overview of my recent work that tackles three important challenges—strategic behavior, interdependence, and online decision making—going beyond standard assumptions. In particular, I will focus on my work establishing the first constant-approximation algorithms for prophet and secretary problems with interdependent values.

Speaker: Robert Samuel (IIT Madras)

Date: Oct 23, 2025

Time: 10:00 AM

Venue: CS26

Abstract:

MLIR (multi-level IR) is making waves due to its applicability in multiple domains, and so much in the ML area that some people call it machine learning IR. It is considered to be a new avatar of LLVM. Robert, whom you know as a TA for our course, has been working on MLIR and has developed a dialect for distributed heterogeneous computing. He is going to teach us the basics of MLIR in this guest lecture in CS6843 Program Analysis.

Speaker: NG Srinivas (IIT Madras)

Date: Oct 15, 2025

Time: 04:00 PM

Venue: CS25

Abstract:

Extended Berkeley Packet Filter (eBPF) has emerged as a powerful method to extend the capabilities of the Linux operating system kernel. eBPF allows users to write code in high-level languages (like C or Rust) and attach them for event-triggered execution at specific execution hooks in the kernel. Among many others, examples of prominent hooks include the network device driver, process scheduler, and the system call dispatcher. To ensure the safe execution of a user-developed eBPF program within the kernel, Linux uses an in-kernel static code analyzer. The analyzer allows a program to execute within the kernel only if it can formally prove that the program is crash-free, always accesses memory within safe bounds, and avoids leaking sensitive kernel data for any input. eBPF has found production-grade deployment is all the hyperscalars as well as several major computing organizations, with some companies anecdotally running dozens of programs on every single server in their fleet. Typical use cases include fleet-wide observability and profiling, flexible and efficient container networking, high-speed connection load balancing, and system call security. This talk will introduce eBPF in concept, provide an overview of the eBPF static code analyzer---the cornerstone of safe kernel software extensibility, and show a short demonstration with real eBPF programs. Time permitting, I will introduce recent research from my group on foundational scientific questions surrounding this technology.

Speaker: Sreejith K. Pallathumadam

Date: Sep 30, 2025

Time: 03:30 PM

Venue: CSB 34

Abstract:

A total coloring of a simple undirected graph $G$ is an assignment of colors to its vertices and edges such that the colors assigned to the vertices form a proper vertex coloring, the colors assigned to the edges form a proper edge coloring, and the color of every edge is different from that of its ends. It is easy to verify that $G$ needs at least $Delta + 1$ colors for any total coloring of $G$ where $Delta$ is the maximum degree of $G$. Surprisingly, Behzad (emph{PhD Thesis, Michigan State University, 1965}) and Vizing (emph{Russian Mathematical Surveys, 1968}) independently conjectured that $Delta + 2$ colors are sufficient. Note that a triangle needs only $Delta + 1$ (i.e. three) colors for a total coloring while a 4-cycle requires $Delta + 2$ (i.e. four) colors. Interestingly, the conjecture is still open. Given a total coloring of a graph $G$, for each vertex $u$, let $colors(u)$ denote the set comprising the color assigned to $u$ and the colors assigned to the edges incident with $u$. A total coloring of a graph $G$ is emph{Adjacent Vertex Distinguishing (AVD)} if for each $uv in E(G)$, $colors(u) neq colors(v)$. The emph{AVD Total Coloring Conjecture} of Zhang, Chen, Li, Yao, Lu and Wang (emph{Science in China Series A: Mathematics, 2005}) states that every graph $G$ admits an AVD total coloring using at most $Delta + 3$ colors. It is easy to verify that a triangle requires $Delta + 3$ (i.e. five) colors for an AVD total coloring. For $s in mathbb{N}$, a graph $G$ is $s$-degenerate if every subgraph of $G$ has a vertex of degree at most $s$. For example, forests are 1-degenerate (what about the converse?), outerplanar graphs are 2-degenerate, triangle-free planar graphs are 3-degenerate and planar graphs are 5-degenerate. Miao, Shi, Hu and Luo (emph{Discrete Mathematics, 2016}) proved the AVD Total Coloring Conjecture for 2-degenerate graphs. We recently proved the conjecture for 3-degenerate graphs; in this talk, we shall discuss this result.