| Title | : | Designing Interconnects and Schedulers for Next-Generation Computing Systems |
| Speaker | : | Dr. Abhijit Das (UPC Barcelona) |
| Details | : | Wed, 5 Mar, 2025 2:00 PM @ Online |
| Abstract: | : | With the anticipated end of Moore's Law, computing system design is undergoing a transformative shift toward chiplet-based architectures and domain-specific acceleration. However, this shift has moved the primary bottleneck from computation to communication, making efficient on-chip and on-package interconnects crucial for system performance. Additionally, as workloads grow increasingly complex, intelligent scheduling strategies become vital for optimising both communication and computation. This talk will first present a novel approach to reducing cache miss penalties in data-intensive applications by leveraging underutilised Network-on-Chip (NoC) router resources, such as input ports and trace buffers. The second part will introduce an open-source design-space exploration framework for multi-objective hardware-mapping co-optimisation of multi-DNN workloads on chiplet-based accelerators. These independent yet critical advancements contribute to improving the performance and efficiency of next-generation computing systems.
Speaker Biodata: Dr. Abhijit Das earned his PhD from IIT Guwahati in 2021. He then spent a year as a postdoc researcher at INRIA France. Since March 2023, he has been serving as the Director of Research at the NaNoNetworking Center, UPC Barcelona. His research interests include networks-on-chip (NoC), package-scale interconnects, multi-accelerator systems, security-focussed NoC designs. |
