Prashanth L.A.
2023-09-11
OS illusion: memory virtualization
Mechanism: Address translation
Approaches
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divide (virtual) address space into fixed-sized units (pages)
physical memory is also split into fixed-sized units (page frames)
Segmentation: variable size (code, stack, heap)
Page table per process is needed to translate the virtual address to physical address
(Virtual Page 0 → Physical Frame 3), (VP 1 → PF 7), (VP 2 → PF 5), and (VP 3 → PF 2)
movl <virtual address>, %eax
Address space \(= 64\) bytes, so \(6\) bits needed
Page size \(= 16\) bytes, so first two bits give VPN
VPN \(\rightarrow\) virtual page number, Offset: offset within the page
movl 21, %eax
32-bit address space, 4KB pages \(\Rightarrow\) 20-bit VPN and 12-bit offset
20-bit VPN \(\Rightarrow 2^{20}\) translations
4 bytes/page table entry (PTE) \(\Rightarrow 4MB\) of memory needed for each page table!
\(100\) processes would need 400MB of memory just for all those address translations!
Bottomline: Cannot store page tables in MMU of HW
Bit | Description |
---|---|
Valid bit | Indicating whether the particular translation is valid |
Protection bit | Indicating whether the page could be read from, written to, or executed from |
Present bit | Indicating whether this page is in physical memory or on disk |
Dirty bit | Indicating whether the page has been modified since it was brought into memory |
Reference bit | Indicating that a page has been accessed |
P: present, R/W: read/write, U/S: supervisor, A: accessed bit, D: dirty bit, PFN: the page frame number
// Extract the VPN from the virtual address
VPN = (VirtualAddress & VPN_MASK) >> SHIFT
// Form the address of the page-table entry (PTE)
PTEAddr = PTBR + (VPN * sizeof(PTE))
// Fetch the PTE
PTE = AccessMemory(PTEAddr)
// Check if process can access the page
if (PTE.Valid == False)
RaiseException(SEGMENTATION_FAULT)
else if (CanAccess(PTE.ProtectBits) == False)
RaiseException(PROTECTION_FAULT)
else
// Access is OK: form physical address and fetch it
offset = VirtualAddress & OFFSET_MASK
PhysAddr = (PTE.PFN << PFN_SHIFT) | offset
Register = AccessMemory(PhysAddr)
To find a location of the desired PTE, the starting location of the page table is needed
For every memory reference, paging requires the OS to perform one extra memory reference
Done on the board