|Title||:||SkipCache: application aware cache management for chip multi-processors|
|Speaker||:||Tripti S. Warrier (IITM)|
|Details||:||Tue, 26 May, 2015 10:00 AM @ BSB 361|
|Abstract:||:||With the advent of multiple cores on a single chip, it is common for the systems to have multi-level caches. Multiple levels of cache reduce the pressure on the memory bandwidth by allowing applications to store their frequently accessed data in them. The levels of cache nearer to the core filter the locality in the application access, which can result in high miss rates at farther levels. This piece of work revolves around one question: Are all levels of cache needed by all applications during all phases of their execution?
The effect of 2-level and 3-level cache hierarchy on the performance of different applications is observed and based on it, we propose an application aware cache management policy called SkipCache. SkipCache allows an application to choose a 2-level or 3-level cache hierarchy during run-time. It dynamically tracks the applications at shared last level cache (LLC) to identify the applications that do not get advantage by using the LLC. Such applications can completely skip the LLC so that other co-scheduled cache friendly applications can e efficiently use it. Evaluation of SkipCache in a 4-core chip multi- processor (CMP) with multi-programmed workloads shows significant performance improvement. SkipCache is orthogonal to other cache management techniques and can be used along with other optimization techniques to improve the system performance.