|Title||:||Low cost router micro-architecture for Network on-Chip|
|Speaker||:||Rathod Nihar Bipinchandra (IITM)|
|Details||:||Tue, 19 Aug, 2014 3:00 PM @ BSB 361|
|Abstract:||:||Network on Chip(NoC) architectures are widely accepted as effective communication fabric to handle large and high performance Chip Multi-Processor (CMP) systems. Chip designers are use more processing elements on a single chip to gain performance by exploiting parallelism. As core count in increases, design complexity, area and power consumption have become serious concern for scalable multi-core systems. Enhancing performance of NoCs under strict area and power budgets is of practical concern. Many low cost router micro-architecture have been proposed with simple design, which consumes less power and area but at the cost of increase in the average latency of the network.
In this work, we analysed the existing low cost router for unidirectional torus topology. We identified the scenarios that affects the performance of the router. We have optimized the router design and proposed CAERUS router micro-architecture. CAERUS design has an effective ejection policy, which avoids unnecessary traversals and an arbitration policy, which balances the opportunity for progress among the router. Experimental results show that, compared to the existing low-cost router designs, CAERUS reduces the traversal latency of the flits in the network and sustain the throughput at higher injection rates. The area and power expenditures are comparable to the existing low cost router architectures.