|Title||:||Efficient Persist Barriers for Multicores|
|Speaker||:||Vijay Nagarajan (School of Informatics, University of Edinburgh, UK)|
|Details||:||Thu, 7 Jan, 2016 11:30 AM @ BSB 361|
|Abstract:||:||Emerging non-volatile memory technologies enable fast, fine-grained persistence compared to slow block-based devices. In order to ensure consistency of persistent state, dirty cache lines need to be periodically flushed from caches and made persistent. A persist barrier is one mechanism for enforcing this ordering. In this talk, I will first show that existing persist barrier implementations, owing to certain ordering dependencies, add cache line flushes to the critical path. I will then introduce an efficient persist barrier, that reduces the number of cache line flushes happening in the critical path. Experimental evaluations using micro-benchmarks and multi-threaded workloads show that using our persist barrier improves performance by around 20% over the state-of-the-art. This is joint work with Arpit Joshi, Marcelo Cintra and Stratis Viglas. For more details: see the paper.
Brief Bio-data: Vijay Nagarajan is an Associate Professor in the School of Informatics, University of Edinburgh. He received his PhD from University of California Riverside under the guidance of Prof. Rajiv Gupta. His research interests broadly span the areas of computer architecture and compilers.